公开(公告)号：US08947968B2

公开(公告)日：2015-02-03

申请号：US13936512

申请日：2013-07-08

申请人： ARM Limited

发明人： Wang-Kun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Gus Yeung

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C11/417 ,  G11C5/148

摘要： A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the bitlines to a given voltage level. During the power saving mode the bitlines are isolated from the precharge node. Voltage control circuitry is provided to maintain the precharge node at a first voltage level during the normal mode and at a second voltage level less than the first voltage level during the power saving mode. By reducing the voltage level at the precharge node during the power saving mode, the amount of inrush current occurring when switching from power saving mode to normal mode can be reduced, and this enables the wakeup time to be reduced when returning from power saving mode to normal mode.

摘要翻译： 存储器具有正常模式和省电模式。 存储器具有位线预充电电路，其在正常模式期间选择性地将一对位线耦合到预充电节点，以将位线充电到给定的电压电平。 在省电模式期间，位线与预充电节点隔离。 提供电压控制电路以在正常模式期间将预充电节点保持在第一电压电平，并且在省电模式期间处于小于第一电压电平的第二电压电平。 通过在省电模式下减小预充电节点处的电压电平，可以减少从省电模式切换到正常模式时所产生的浪涌电流量，并且能够在从省电模式返回时减少唤醒时间 正常模式。

公开(公告)号：US20140269091A1

公开(公告)日：2014-09-18

申请号：US13827815

申请日：2013-03-14

申请人： ARM LIMITED

发明人： Bo ZHENG ,  Gus Yeung ,  Fakhruddin ali Bohra

IPC分类号： G11C16/28

CPC分类号： G11C16/28 ,  G11C7/12 ,  G11C8/08 ,  G11C11/418 ,  G11C11/419

摘要： A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column has an active mode of operation where a read operation may be performed on an activated memory cell within that column group, and a non-active mode of operation where the read operation is not performable. Precharge circuitry is used, for each column group, to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell includes coupling circuitry connected between the associated read bit line and a reference line associated with the column group containing that memory cell.

摘要翻译： 存储器装置包括布置成多个行和列的存储器单元的阵列，每行耦合到相关联的读取字线，并且每列形成至少一个列组，其中每个列组的存储单元耦合到 相关的读位线。 每列具有主动操作模式，其中可以对该列组内的激活的存储器单元执行读取操作，以及读操作不可执行的非活动操作模式。 对于每个列组，预充电电路用于在读取操作之前将相关联的读取位线预充电到第一电压电平。 每个存储单元包括连接在相关读取位线和与包含该存储器单元的列组相关联的参考线之间的耦合电路。