公开(公告)号：US09619390B2

公开(公告)日：2017-04-11

申请号：US12649548

申请日：2009-12-30

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/02 ,  G06F12/0862 ,  G06F12/0815

CPC分类号： G06F12/0862 ,  G06F12/0815

摘要： According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular processor core among the multiple processor cores. In response to receipt of the data prefetch request, the memory controller provides a coherency response indicating an excess number of data prefetch requests. In response to the coherency response, the particular processor core reduces a rate of issuance of data prefetch requests.

公开(公告)号：US20110161588A1

公开(公告)日：2011-06-30

申请号：US12649725

申请日：2009-12-30

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams ,  Phillip G. Williams

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams ,  Phillip G. Williams

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0811 ,  G06F9/3834 ,  G06F12/0815 ,  G06F12/0831 ,  Y02D10/13

摘要： In response to a memory access request of a processor core that targets a target cache line, the lower level cache of a vertical cache hierarchy associated with the processor core supplies a copy of the target cache line to an upper level cache in the vertical cache hierarchy and retains a copy in a shared coherence state. The upper level cache holds the copy of the target cache line in a private shared ownership coherence state indicating that each cached copy of the target memory block is cached within the vertical cache hierarchy associated with the processor core. In response to the upper level cache signaling replacement of the copy of the target cache line in the private shared ownership coherence state, the lower level cache updates its copy of the target cache line to the exclusive ownership coherence state without coherency messaging with other vertical cache hierarchies.

摘要翻译： 响应于针对目标高速缓存线的处理器核心的存储器访问请求，与处理器核心相关联的垂直高速缓存层级的较低级缓存将目标高速缓存行的副本提供给垂直高速缓存层级中的高级缓存 并保留共享一致状态的副本。 高级缓存将目标高速缓存行的副本保存在私有共享所有权一致状态中，指示目标存储器块的每个高速缓存副本被缓存在与处理器核心相关联的垂直高速缓存层级内。 响应于在私有共享所有权相干状态下高级缓存信令替换目标高速缓存行的副本，下级缓存将其目标高速缓存行的副本更新为独占所有权相干状态，而不与其他垂直高速缓存的一致性消息传递 层次结构。

公开(公告)号：US20080086605A1

公开(公告)日：2008-04-10

申请号：US11952596

申请日：2007-12-07

申请人： ROBERT BELL ,  Hugh Shen ,  Jeffrey Stuecheli ,  Derek Williams

发明人： ROBERT BELL ,  Hugh Shen ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F12/16

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F12/0897

摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.

摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

公开(公告)号：US20060179183A1

公开(公告)日：2006-08-10

申请号：US11054372

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F13/161 ,  G11C5/04

摘要： Multiple write buffers are provided within each memory module and are utilized to buffer multiple received write data forwarded to the chip via a write-to-buffer data operation. When a write is received at the memory controller, the memory controller first issues the write-to-buffer (data) operation and the data is forwarded to one of the write buffers. Multiple writes targeting the same DIMM are thus buffered. When all of the available buffers at a memory module are full, the memory controller issues the set of address only write commands to the memory module. The control logic of the DIMM streams all of the buffered write data to the memory device(s) in one continuous burst. By buffering multiple writes and then writing all buffered write data within the DIMM in a single burst, the write-to-read turnaround penalty of the memory module's data bus is substantially minimized.

摘要翻译： 在每个存储器模块内提供多个写入缓冲器，并且用于经由写入缓冲器数据操作来缓冲转发到芯片的多个接收到的写入数据。 当在存储器控制器处接收到写入时，存储器控制器首先发出写入缓冲器（数据）操作，并将数据转发到写入缓冲器之一。 因此，针对同一DIMM的多个写入被缓存。 当内存模块中的所有可用缓冲区都已满时，内存控制器会向内存模块发出一组仅地址写入命令。 DIMM的控制逻辑将所有缓冲的写入数据以一个连续的脉冲串流式传输到存储器件。 通过缓冲多个写入，然后以单个脉冲串将所有缓冲的写入数据写入DIMM内，内存模块的数据总线的写入读取周转损失基本上最小化。

公开(公告)号：US09110808B2

公开(公告)日：2015-08-18

申请号：US12649725

申请日：2009-12-30

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams ,  Phillip G. Williams

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams ,  Phillip G. Williams

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F9/38

CPC分类号： G06F12/0811 ,  G06F9/3834 ,  G06F12/0815 ,  G06F12/0831 ,  Y02D10/13

摘要： In response to a memory access request of a processor core that targets a target cache line, the lower level cache of a vertical cache hierarchy associated with the processor core supplies a copy of the target cache line to an upper level cache in the vertical cache hierarchy and retains a copy in a shared coherence state. The upper level cache holds the copy of the target cache line in a private shared ownership coherence state indicating that each cached copy of the target memory block is cached within the vertical cache hierarchy associated with the processor core. In response to the upper level cache signaling replacement of the copy of the target cache line in the private shared ownership coherence state, the lower level cache updates its copy of the target cache line to the exclusive ownership coherence state without coherency messaging with other vertical cache hierarchies.

摘要翻译： 响应于针对目标高速缓存线的处理器核心的存储器访问请求，与处理器核心相关联的垂直高速缓存层级的较低级缓存将目标高速缓存行的副本提供给垂直高速缓存层级中的高级缓存 并保留共享一致状态的副本。 高级缓存将目标高速缓存行的副本保存在私有共享所有权一致状态中，指示目标存储器块的每个高速缓存副本被缓存在与处理器核心相关联的垂直高速缓存层级内。 响应于在私有共享所有权相干状态下高级缓存信令替换目标高速缓存行的副本，下级缓存将其目标高速缓存行的副本更新为独占所有权相干状态，而不与其他垂直高速缓存的一致性消息传递 层次结构。

公开(公告)号：US20070277026A1

公开(公告)日：2007-11-29

申请号：US11836872

申请日：2007-08-10

申请人： ROBERT BELL ,  Hugh Shen ,  Jeffrey Stuecheli ,  Derek Williams

发明人： ROBERT BELL ,  Hugh Shen ,  Jeffrey Stuecheli ,  Derek Williams

IPC分类号： G06F9/00

CPC分类号： G06F9/3824 ,  G06F9/30043 ,  G06F12/0897

摘要： A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple store operations during a store gathering window to obtain a data portion of a write transaction directed to lower level memory. In addition, the store queue includes dispatch logic that varies a size of the store gathering window to optimize store performance for different store behaviors and workloads.

摘要翻译： 处理器包括执行存储指令以获得存储操作的至少一个指令执行单元和耦合到指令执行单元的存储队列。 存储队列包括队列条目，其中存储队列在存储收集窗口期间收集多个存储操作，以获得指向低级存储器的写入事务的数据部分。 此外，商店队列包括调度逻辑，其改变商店收集窗口的大小以优化针对不同商店行为和工作负载的存储性能。

公开(公告)号：US20060179206A1

公开(公告)日：2006-08-10

申请号：US11054066

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F12/06

CPC分类号： G06F13/1647 ,  G11C5/04 ,  Y02D10/14

摘要： A set of N copies of bank control logic are provided for tracking the banks within the memory modules (DRAMS). When the total number of banks within the memory module(s) is greater than N, the addresses of particular banks are folded into a single grouping. The banks are represented by the N copies of the bank control logic even when the total number of banks is greater than N. Each bank within the group is tagged as being busy when any one of the banks in the group is the target of a memory access request. The algorithm folds the addresses of the banks in an order that substantially minimizes the likelihood that a bank that is in a busy or false busy state will be the target of another memory access request. Power and logic savings are recognized as only N copies of bank control logic have to be supported.

公开(公告)号：US20120203973A1

公开(公告)日：2012-08-09

申请号：US13445646

申请日：2012-04-12

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams ,  Thomas R. Puzak

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams ,  Thomas R. Puzak

IPC分类号： G06F12/12

CPC分类号： G06F12/0811 ,  G06F12/12

摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.

摘要翻译： 数据处理系统包括第一和第二处理单元和系统存储器。 第一处理单元具有第一上层和第一下层高速缓存，第二处理单元具有第二上层和下层高速缓存。 响应于数据请求，选择要从第一较低级高速缓存丢弃的受害者高速缓存行，并且第一较低级高速缓存选择在执行到第二低级高速缓存的受害者高速缓存行的横向流出（LCO） 基于与受害者高速缓存行相关联的置信指示，将受害者缓存行的丢弃发送到系统存储器。 响应于选择LCO，第一处理单元在互连结构上发布LCO命令，并从第一低级缓存中移除受害者高速缓存行，并且第二下级缓存保存受害缓存行。

公开(公告)号：US20110161587A1

公开(公告)日：2011-06-30

申请号：US12649548

申请日：2009-12-30

申请人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams

发明人： Guy L. Guthrie ,  William J. Starke ,  Jeffrey Stuecheli ,  Derek E. Williams

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0815

摘要： According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular processor core among the multiple processor cores. In response to receipt of the data prefetch request, the memory controller provides a coherency response indicating an excess number of data prefetch requests. In response to the coherency response, the particular processor core reduces a rate of issuance of data prefetch requests.

摘要翻译： 根据数据处理的方法，存储器控制器从数据处理系统中的多个处理器核心接收多个数据预取请求，其中多个预取负载请求包括由多处理器中的特定处理器核发出的数据预取请求 核心。 响应于接收到数据预取请求，存储器控制器提供指示多余数据预取请求的一致性响应。 响应于一致性响应，特定处理器核心降低了数据预取请求的发布速率。

公开(公告)号：US20060179248A1

公开(公告)日：2006-08-10

申请号：US11055640

申请日：2005-02-10

申请人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

发明人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F11/1064 ,  G06F12/0831

摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.

摘要翻译： 高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。 系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。 系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。 响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。