公开(公告)号：US20060179248A1

公开(公告)日：2006-08-10

申请号：US11055640

申请日：2005-02-10

申请人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

发明人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F11/1064 ,  G06F12/0831

摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.

摘要翻译： 高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。 系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。 系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。 响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

公开(公告)号：US20080028156A1

公开(公告)日：2008-01-31

申请号：US11836908

申请日：2007-08-10

申请人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

发明人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

IPC分类号： G06F12/08

CPC分类号： G06F11/1064 ,  G06F12/0831

摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.

摘要翻译： 高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。 系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。 系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。 响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

公开(公告)号：US20050132147A1

公开(公告)日：2005-06-16

申请号：US10733948

申请日：2003-12-10

申请人： Ravi Arimilli ,  Sanjeev Ghai ,  Warren Maule

发明人： Ravi Arimilli ,  Sanjeev Ghai ,  Warren Maule

IPC分类号： G06F12/08 ,  G06F9/38 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06

CPC分类号： G06F9/383 ,  G06F9/3832 ,  G06F9/3851 ,  G06F12/0215

摘要： A data processing system includes one or more processing cores, a system memory having multiple rows of data storage, and a memory controller that controls access to the system memory and performs supplier-based memory speculation. The memory controller includes a memory speculation table that stores historical information regarding prior memory accesses. In response to a memory access request, the memory controller directs an access to a selected row in the system memory to service the memory access request. The memory controller speculatively directs that the selected row will continue to be energized following the access based upon the historical information in the memory speculation table, so that access latency of an immediately subsequent memory access is reduced.

摘要翻译： 数据处理系统包括一个或多个处理核心，具有多行数据存储的系统存储器，以及控制对系统存储器的访问并执行基于供应商的存储器推测的存储器控​​制器。 存储器控制器包括存储有关先前存储器访问的历史信息的存储器推测表。 响应于存储器访问请求，存储器控制器引导对系统存储器中的所选行的访问以服务存储器访问请求。 存储器控制器推测地指示在基于存储器推测表中的历史信息的访问之后，所选择的行将继续被通电，使得紧随其后的存储器访问的访问等待时间减少。

公开(公告)号：US20080091906A1

公开(公告)日：2008-04-17

申请号：US11951752

申请日：2007-12-06

申请人： Mark Brittain ,  Edgar Cordero ,  Sanjeev Ghai ,  Warren Maule

发明人： Mark Brittain ,  Edgar Cordero ,  Sanjeev Ghai ,  Warren Maule

IPC分类号： G06F12/00

CPC分类号： A61C17/349 ,  A61C17/3436 ,  Y10T29/49826

摘要： A memory subsystem completes multiple read operations in parallel, utilizing the functionality of buffered memory modules in a daisy chain topology. A variable read latency is provided with each read command to enable memory modules to run independently in the memory subsystem. Busy periods of the memory device architecture are hidden by allowing data buses on multiple memory modules attached to the same data channel to run in parallel rather than in series and by issuing reads earlier than required to enable the memory devices to return from a busy state earlier. During scheduling of reads, the earliest received read whose target memory module is not busy is immediately issued at a next command cycle. The memory controller provides a delay parameter with each issued read. The number of cycles of delay is calculated to allow maximum utilization of the memory modules' data bus bandwidth without causing collisions on the memory channel.

摘要翻译： 存储器子系统并行完成多个读取操作，利用菊花链拓扑中的缓冲存储器模块的功能。 每个读取命令都提供了一个变量读取延迟，以使内存模块能够在存储器子系统中独立运行。 通过允许连接到同一数据通道的多个存储器模块上的数据总线并行运行而不是串行运行并且通过发出早于使存储器件从繁忙状态返回的所需的读数来隐藏存储器件架构的繁忙期 。 在读取调度期间，目标存储器模块不忙的最早接收到的读取将在下一个命令周期立即发出。 存储器控制器为每个发出的读取提供延迟参数。 计算延迟的周期数以允许最大限度地利用存储器模块的数据总线带宽而不引起存储器通道上的冲突。

公开(公告)号：US20060179262A1

公开(公告)日：2006-08-10

申请号：US11054446

申请日：2005-02-09

申请人： Mark Brittain ,  Edgar Cordero ,  Sanjeev Ghai ,  Warren Maule

发明人： Mark Brittain ,  Edgar Cordero ,  Sanjeev Ghai ,  Warren Maule

IPC分类号： G06F13/28

CPC分类号： G06F13/1631

摘要： A memory subsystem completes multiple read operations in parallel, utilizing the functionality of buffered memory modules in a daisy chain topology. A variable read latency is provided with each read command to enable memory modules to run independently in the memory subsystem. Busy periods of the memory device architecture are hidden by allowing data buses on multiple memory modules attached to the same data channel to run in parallel rather than in series and by issuing reads earlier than required to enable the memory devices to return from a busy state earlier. During scheduling of reads, the earliest received read whose target memory module is not busy is immediately issued at a next command cycle. The memory controller provides a delay parameter with each issued read. The number of cycles of delay is calculated to allow maximum utilization of the memory modules' data bus bandwidth without causing collisions on the memory channel.

摘要翻译： 存储器子系统并行完成多个读取操作，利用菊花链拓扑中的缓冲存储器模块的功能。 每个读取命令都提供了一个变量读取延迟，以使内存模块能够在存储器子系统中独立运行。 通过允许连接到同一数据通道的多个存储器模块上的数据总线并行运行而不是串行运行并且通过发出早于使存储器件从繁忙状态返回的读取的读取来隐藏存储器设备架构的繁忙周期 。 在读取调度期间，目标存储器模块不忙的最早接收到的读取将在下一个命令周期立即发出。 存储器控制器为每个发出的读取提供延迟参数。 计算延迟的周期数以允许最大限度地利用存储器模块的数据总线带宽而不引起存储器通道上的冲突。

公开(公告)号：US20060179362A1

公开(公告)日：2006-08-10

申请号：US11054417

申请日：2005-02-09

申请人： Luiz Alves ,  Mark Brittain ,  Timothy Dell ,  Sanjeev Ghai ,  Warren Maule ,  Scott Swaney

发明人： Luiz Alves ,  Mark Brittain ,  Timothy Dell ,  Sanjeev Ghai ,  Warren Maule ,  Scott Swaney

IPC分类号： G06F11/00

CPC分类号： G11C29/42 ,  G06F11/1044 ,  G11C5/04 ,  G11C29/4401 ,  G11C29/76 ,  G11C29/846 ,  G11C2029/0409

摘要： A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.

摘要翻译： 提出了一种用于校正双列直插式存储器模块（DIMM）中的主动态随机存取存储器（DRAM）中的数据错误的方法和系统。 每个DRAM具有左半部分（用于存储位0：3）和右半部分（用于存储位4：7）。 确定数据错误是在主DRAM的左半还是右半部。 发生错误的主要DRAM的一半从服务中删除。 原始存储在主DRAM缺陷半部分的数据的所有后续读取和写入都被制成DIMM中的备用DRAM的一半，而DRAM的无缺陷半部分继续用于随后存储数据。

公开(公告)号：US20050132148A1

公开(公告)日：2005-06-16

申请号：US10733953

申请日：2003-12-10

申请人： Ravi Arimilli ,  Sanjeev Ghai ,  Warren Maule

发明人： Ravi Arimilli ,  Sanjeev Ghai ,  Warren Maule

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0215 ,  G06F12/0831 ,  G06F2212/507

摘要： A data processing system includes a system memory, one or more processing cores, and a memory controller that controls access to a system memory. The memory controller includes a memory speculation mechanism that stores historical information regarding prior memory accesses. In response to a memory access request, the memory controller speculatively initiates access to the system memory based upon the historical information in the memory speculation mechanism in advance of receipt of a coherency message indicating that the memory access request is to be serviced by reference to the system memory.

摘要翻译： 数据处理系统包括系统存储器，一个或多个处理核心以及控制对系统存储器的访问的存储器控​​制器。 存储器控制器包括存储器推测机制，其存储关于先前存储器访问的历史信息。 响应于存储器访问请求，存储器控制器基于存储器推测机制中的历史信息推测地启动对系统存储器的访问，在接收到指示将通过参考的存储器访问请求被服务的一致性消息之前 系统内存

公开(公告)号：US20060179183A1

公开(公告)日：2006-08-10

申请号：US11054372

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F13/161 ,  G11C5/04

摘要： Multiple write buffers are provided within each memory module and are utilized to buffer multiple received write data forwarded to the chip via a write-to-buffer data operation. When a write is received at the memory controller, the memory controller first issues the write-to-buffer (data) operation and the data is forwarded to one of the write buffers. Multiple writes targeting the same DIMM are thus buffered. When all of the available buffers at a memory module are full, the memory controller issues the set of address only write commands to the memory module. The control logic of the DIMM streams all of the buffered write data to the memory device(s) in one continuous burst. By buffering multiple writes and then writing all buffered write data within the DIMM in a single burst, the write-to-read turnaround penalty of the memory module's data bus is substantially minimized.

摘要翻译： 在每个存储器模块内提供多个写入缓冲器，并且用于经由写入缓冲器数据操作来缓冲转发到芯片的多个接收到的写入数据。 当在存储器控制器处接收到写入时，存储器控制器首先发出写入缓冲器（数据）操作，并将数据转发到写入缓冲器之一。 因此，针对同一DIMM的多个写入被缓存。 当内存模块中的所有可用缓冲区都已满时，内存控制器会向内存模块发出一组仅地址写入命令。 DIMM的控制逻辑将所有缓冲的写入数据以一个连续的脉冲串流式传输到存储器件。 通过缓冲多个写入，然后以单个脉冲串将所有缓冲的写入数据写入DIMM内，内存模块的数据总线的写入读取周转损失基本上最小化。

公开(公告)号：US20080091905A1

公开(公告)日：2008-04-17

申请号：US11951735

申请日：2007-12-06

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F13/1626

摘要： Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.

摘要翻译： 内存模块设计有多个写入缓冲器，用于临时保存写入数据。 “写入缓冲”操作将内存控制器中的写入数据移动到写入缓冲区，同时内存模块正忙于处理读取操作。 然后，随后发出仅地址的“写入”命令来将缓冲的写入数据写入存储器件。 针对闲置DIMM的写命令在针对繁忙DIMM（或即将忙于）的写入之前按顺序发出。 通过后台写入缓冲操作移动数据可以提高通用写入数据通道的效率，并允许写入数据总线在重读操作期间达到最大带宽。 实际写入操作，延迟到写入负面影响的时期可以完全/大部分隐藏。 在光读取活动期间，或者当没有读取待处理时，缓冲存储器模块中的数据使缓冲数据能够同时跨多个存储器模块并行编写。

公开(公告)号：US20060179213A1

公开(公告)日：2006-08-10

申请号：US11054447

申请日：2005-02-09

申请人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

发明人： Mark Brittain ,  Warren Maule ,  Gary Morrison ,  Jeffrey Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G06F13/1626

摘要： Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.

摘要翻译： 内存模块设计有多个写入缓冲器，用于临时保存写入数据。 “写入缓冲”操作将内存控制器中的写入数据移动到写入缓冲区，同时内存模块正忙于处理读取操作。 然后，随后发出仅地址的“写入”命令来将缓冲的写入数据写入存储器件。 针对闲置DIMM的写命令在针对繁忙DIMM（或即将忙于）的写入之前按顺序发出。 通过后台写入缓冲操作移动数据可以提高通用写入数据通道的效率，并允许写入数据总线在重读操作期间达到最大带宽。 实际写入操作，延迟到写入负面影响的时期可以完全/大部分隐藏。 在光读取活动期间，或者当没有读取待处理时，缓冲存储器模块中的数据使缓冲数据能够同时跨多个存储器模块并行编写。