公开(公告)号：US11217150B2

公开(公告)日：2022-01-04

申请号：US16485994

申请日：2018-09-06

Applicant: BOE Technology Group Co., Ltd.

Inventor： Mingfu Han ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/32

Abstract: The present application discloses a gate driver on array (GOA) circuit of a display panel. The GOA circuit includes a first GOA unit comprising a unit-circuitry structure having a pull-up node commonly coupled to three output transistors to control outputting of a first set of three gate-driving signals respectively to a first set of three gate lines associated with the display panel. The GOA circuit additionally includes a second GOA unit comprising a substantially same unit-circuitry structure cascaded with the first GOA unit and configured to control outputting a second set of three gate-driving signals respectively to a second set of three gate lines associated with the display panel. Moreover, the GOA circuit includes a capacitor connected from one in the second set of three output terminals of the second GOA unit to the pull-up node of the first GOA unit.

公开(公告)号：US20210356785A1

公开(公告)日：2021-11-18

申请号：US16344023

申请日：2018-09-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lijun Yuan ,  Mingfu Han ,  Haoliang Zheng ,  Guangliang Shang ,  Xing Yao ,  Shunhang Zhang

IPC: G02F1/1368 ,  G02F1/133

Abstract: The present application discloses a pixel array substrate. The pixel array substrate includes a plurality of pixels arranged in an array having multiple data-input terminals. N columns of subpixels per each column of pixels are associated with N sets of M numbers of data lines. N is an integer equal to and greater than 1 and M is an even number equal to or greater than 2. The pixel array substrate also includes N sets of M numbers of switches coupled respectively to the N sets of M numbers of data lines. Control terminals of each set of M numbers of switches are respectively coupled to M numbers of clock-signal terminals to receive respective clock control signals to control M groups of subpixels in each corresponding one column of subpixels for connecting with one of the multiple data-input terminals respectively via each corresponding set of M numbers of data lines.

公开(公告)号：US11012274B2

公开(公告)日：2021-05-18

申请号：US16414478

申请日：2019-05-16

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lijun Yuan ,  Haoliang Zheng ,  Guangliang Shang ,  Xing Yao ,  Mingfu Han

IPC: H04L27/26 ,  H03D1/22

Abstract: A demultiplexer includes a voltage boost circuit and at least one data selection output circuit. The voltage boost circuit is coupled to N second-stage selection signal input terminals and N first-stage selection signal input terminals, N is greater than or equal to 2, and N is a positive integer. Each data selection output circuit is coupled to a data input terminal, N data output terminals and the N first-stage selection signal input terminals.

公开(公告)号：US10991289B2

公开(公告)日：2021-04-27

申请号：US16346962

申请日：2018-09-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Chengyou Han ,  Mingfu Han ,  Lijun Yuan ,  Xing Yao ,  Haoliang Zheng

IPC: G09G3/20

Abstract: The present disclosure is related to a memory-in-pixel circuit. The memory-in-pixel circuit comprises a switch sub-circuit, and a data input sub-circuit. The data input sub-circuit comprises a first floating gate transistor and a second floating gate transistor. The data input sub-circuit is configured to transmit a data signal from one of a plurality of data lines to a pixel electrode under control of the switch sub-circuit.

公开(公告)号：US10902810B2

公开(公告)日：2021-01-26

申请号：US15751066

申请日：2017-07-28

Applicant: BOE Technology Group Co., Ltd.

Inventor： Mingfu Han ,  Guangliang Shang ,  Xing Yao ,  Seung Woo Han ,  Jiha Kim ,  Haoliang Zheng ,  Lijun Yuan ,  Zhichong Wang

IPC: G09G3/36

Abstract: The present disclosure relates to an array substrate gate driving unit and an apparatus thereof, a driving method and a display apparatus. The array substrate gate driving unit includes: an input circuit, connected with an input signal terminal and a pull-up node PU; a pull-down circuit, connected with a first voltage signal terminal and the pull-up node PU; a pull-down control circuit, connected with the pull-down circuit via a pull-down node PD; an output circuit, connected with a clock signal terminal CLK, a second voltage signal terminal and a control circuit; a reset circuit, connected with a reset signal terminal Reset, the first voltage signal terminal and the pull-up node PU; and the control circuit, connected with the pull-up node PU and the output circuit.

公开(公告)号：US10818239B2

公开(公告)日：2020-10-27

申请号：US16399612

申请日：2019-04-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lijun Yuan ,  Guangliang Shang ,  Xing Yao ,  Haoliang Zheng ,  Mingfu Han

IPC: G09G3/3258 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  H01L27/32

Abstract: The present disclosure provides a pixel driving circuit and a method for driving the same, a pixel unit, and a display panel. The pixel circuit includes: a driving sub-circuit, configured to generate driving current based on a data signal and a first voltage; a first light-emitting control sub-circuit configured to receive a first control signal and the first voltage, and provide the first voltage to the driving sub-circuit under control of the first control signal; a second light-emitting control sub-circuit configured to receive a second control signal and provide driving current generated by the driving sub-circuit to an output terminal of the pixel driving circuit under control of the second control signal; a driving control sub-circuit configured to receive the second control signal and the data signal and provide the data signal to the driving sub-circuit under control of the second control signal; and a reset sub-circuit configured to receive a reset signal and a second voltage, and reset the driving sub-circuit using the second voltage under control of the reset signal.

公开(公告)号：US10755665B2

公开(公告)日：2020-08-25

申请号：US16450226

申请日：2019-06-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungwoo Han ,  Guangliang Shang

IPC: G09G3/36 ,  G02F1/1362 ,  G02F1/1368

Abstract: A pixel circuit, an array substrate, a display panel and an electronic apparatus are provided. The pixel circuit includes: a data writing sub-circuit, a first data storage sub-circuit, a second data storage sub-circuit and a light-emitting control sub-circuit. The data writing sub-circuit writes, under the control of a signal input from a first control signal input end, to the first data storage sub-circuit a data signal input from a data signal input end, and writes, under the control of a signal input from a second control signal input end, to the second data storage sub-circuit the data signal input from the data signal input end. The light-emitting control sub-circuit controls on/off states of corresponding thin film transistors in accordance with data signals output from the first data storage sub-circuit and the second data storage sub-circuit, so that different gray-scales may be rendered.

公开(公告)号：US20200265763A1

公开(公告)日：2020-08-20

申请号：US16346962

申请日：2018-09-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Chengyou Han ,  Mingfu Han ,  Lijun Yuan ,  Xing Yao ,  Haoliang Zheng

IPC: G09G3/20

Abstract: The present disclosure is related to a memory-in-pixel circuit. The memory-in-pixel circuit comprises a switch sub-circuit, and a data input sub-circuit. The data input sub-circuit comprises a first floating gate transistor and a second floating gate transistor. The data input sub-circuit is configured to transmit a data signal from one of a plurality of data lines to a pixel electrode under control of the switch sub-circuit.

公开(公告)号：US10679565B2

公开(公告)日：2020-06-09

申请号：US16063448

申请日：2017-11-07

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiha Kim ,  Seung Woo Han ,  Guangliang Shang ,  Haoliang Zheng ,  Xing Yao ,  Mingfu Han ,  Zhichong Wang ,  Lijun Yuan ,  Yun Sik Im ,  Yinglong Huang ,  Xue Dong

IPC: G09G3/3266 ,  G11C19/28 ,  H01L27/12 ,  G09G3/3208

Abstract: An array substrate, a display panel, a display device and a driving method. The array substrate includes: a plurality of first pixel units arranged in an array in a first region; a first gate driving circuit a second gate driving circuit; a plurality of first gate lines connected with the first gate driving circuit; and a plurality of second gate lines connected with the second gate driving circuit. A first portion of the plurality of first pixel units is connected with the plurality of first gate lines, and each first pixel unit in the first portion is connected with one of the plurality of first gate lines; and a second portion of the plurality of first pixel units is connected with the plurality of second gate lines, and each first pixel unit in the second portion is connected with one of the plurality of second gate lines.

公开(公告)号：US10235919B2

公开(公告)日：2019-03-19

申请号：US15577402

申请日：2017-05-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Xing Yao ,  Mingfu Han ,  Seung-Woo Han ,  Yun-Sik Im ,  Jing Lv ,  Yinglong Huang ,  Jung-Mok Jun ,  Xue Dong ,  Haoliang Zheng ,  Lijun Yuan ,  Zhichong Wang ,  Ji Ha Kim

IPC: G09G3/20 ,  G11C19/28

Abstract: A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.