公开(公告)号：US5896399A

公开(公告)日：1999-04-20

申请号：US763493

申请日：1996-12-11

申请人： George McNeil Lattimore ,  Michael Kevin Ciraula ,  Dieter F. Wendel ,  Manoj Kumar ,  Friedrich-Christian Wernicke

发明人： George McNeil Lattimore ,  Michael Kevin Ciraula ,  Dieter F. Wendel ,  Manoj Kumar ,  Friedrich-Christian Wernicke

IPC分类号： G11C29/14 ,  G11C29/00

CPC分类号： G11C29/14

摘要： The present invention applies a Static Evaluate technique to a memory array in a selective manner that allows some parts of the array to use the technique, and yet keeps the array area and timing unaffected for normal operation. The present invention allows the decode functions of the memory array to become pseudo-static during a first part of a clock cycle. In addition, if a write function is being performed, the write data is also held pseudo-static and is not written until a second part of a clock cycle when all addresses and data have stabilized. The invention can be used for system debug, product bring-up, or burn-in, even if there are non-functional race paths. A system and method of testing and burning in self-timed memory arrays includes a Static Evaluate circuit applied to the decoding function and the writing function of the array, a circuit for holding an address or write data inactive for the first part of a cycle, a circuit for activating the address or write data for the second part of a cycle, and a circuit for ensuring that the array resets correctly.

摘要翻译： 本发明以选择性方式将静态评估技术应用于存储器阵列，其允许阵列的某些部分使用该技术，并且仍保持阵列区域和定时不受正常操作的影响。 本发明允许存储器阵列的解码功能在时钟周期的第一部分期间变为伪静态。 此外，如果正在执行写入功能，则写入数据也保持为伪静态，并且在所有地址和数据均已稳定时，不会写入时钟周期的第二部分。 即使存在非功能性赛跑路径，本发明也可用于系统调试，产品开机或老化。 在自定时存储器阵列中测试和刻录的系统和方法包括应用于解码功能的静态评估电路和阵列的写入功能，用于保持地址或写入对于循环的第一部分无效的数据的电路， 用于激活用于周期的第二部分的地址或写入数据的电路，以及用于确保阵列正确复位的电路。

公开(公告)号：US5892725A

公开(公告)日：1999-04-06

申请号：US78248

申请日：1998-05-13

申请人： George McNeil Lattimore ,  Younes Lotfi ,  Robert Anthony Ross, Jr. ,  Gus Wai-Yen Yeung

发明人： George McNeil Lattimore ,  Younes Lotfi ,  Robert Anthony Ross, Jr. ,  Gus Wai-Yen Yeung

IPC分类号： G11C5/06 ,  G11C7/18 ,  G11C8/00

CPC分类号： G11C5/063 ,  G11C7/18

摘要： A memory and a method for communicating therewith are implemented, the memory having a plurality of memory cell groups. Each memory cell group contains a plurality of memory cells. Memory cell groups within each subset of a plurality of subsets of memory cell groups include the same predetermined number of memory cells. During a read operation, a local bitline associated with the memory cell group from which data is being read is coupled to a global bitline. Other local bitlines, associated with the memory cell groups not being accessed during the read are decoupled from the global bitlines. Following a read, the local and global bitlines are restored by a precharge operation.

摘要翻译： 实现与其通信的存储器和方法，该存储器具有多个存储单元组。 每个存储单元组包含多个存储单元。 存储器单元组的多个子集的每个子集内的存储单元组包括相同的预定数量的存储器单元。 在读取操作期间，与正在读取数据的存储器单元组相关联的本地位线被耦合到全局位线。 与读取期间未被访问的存储器单元组相关联的其他本地位线与全局位线分离。 读取后，通过预充电操作恢复本地和全局位线。

公开(公告)号：US5892704A

公开(公告)日：1999-04-06

申请号：US52245

申请日：1998-03-31

申请人： George McNeil Lattimore ,  Robert Anthony Ross, Jr. ,  Gus Wai-Yen Yeung

发明人： George McNeil Lattimore ,  Robert Anthony Ross, Jr. ,  Gus Wai-Yen Yeung

IPC分类号： G11C8/08 ,  G11C5/06

CPC分类号： G11C8/08

摘要： A memory array of a plurality of memory cells accessed by either a single-ended wordline or a differential pair of wordlines emanating from a wordline decoder is improved by the inclusion of a sense amplifier circuit on the far end of the memory array from the wordline decoder, which operates to amplify the wordline signals.

摘要翻译： 通过在字线解码器的存储器阵列的远端包括读出放大器电路，可以通过从字线解码器发出的单端字线或字线的差分对访问的多个存储器单元的存储器阵列得到改善 ，其操作以放大字线信号。

公开(公告)号：US5892372A

公开(公告)日：1999-04-06

申请号：US790262

申请日：1997-01-27

申请人： Michael Kevin Ciraula ,  George McNeil Lattimore ,  Robert Paul Masleid ,  Donald George Mikan, Jr.

发明人： Michael Kevin Ciraula ,  George McNeil Lattimore ,  Robert Paul Masleid ,  Donald George Mikan, Jr.

IPC分类号： H03K19/096

CPC分类号： H03K19/0963

摘要： A method and implementing structures for a domino block circuit configuration includes a plurality of domino logic blocks including inverter circuits to provide inverted signals which are needed for a comprehensive logic analysis and processing. A plurality of clocking signals are applied at various clocking inputs throughout the circuit. The clocking signals are timed relative to each other in a timing sequence to assure that the logic circuit evaluations occur only after relevant data and switching signals have stabilized.

摘要翻译： 多米诺骨牌电路配置的方法和实现结构包括多个多米诺骨牌逻辑块，包括用于提供综合逻辑分析和处理所需的反相信号的反相器电路。 在整个电路中的各种时钟输入端施加多个时钟信号。 时钟信号在定时序列中相对于彼此定时，以确保逻辑电路评估仅在相关数据和切换信号已经稳定之后才发生。