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公开(公告)号：US5963486A
公开(公告)日：1999-10-05
申请号：US100354
申请日：1998-06-19
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/065 , G11C11/4096 , G11C7/1048 , G11C7/12
摘要： A bit switch circuit (10) includes an amplifier stage (11) and a plurality of input stages (23,33,43,53). Each input stage (23,33,43,53) is connected to receive as inputs the signals applied to a bit line pair associated with a memory array. Each input stage (23,33,43,53) is also associated with a common node (24,34,44,54), and a select transistor (T4, T5, T6, T7). Each select transistor (T4, T5, T6, T7) responds to a select input signal to couple the respective common node (24,34,44,54) to ground. This allows the sense amplifier (11) to respond to the data signals on the bit line pair (20,21,30,31,40,41,50,51) associated with the respective input stage (23,33,43,53).
摘要翻译： 位开关电路（10）包括放大器级（11）和多个输入级（23,33,43,53）。 每个输入级（23,33,43,53）被连接以接收施加到与存储器阵列相关联的位线对的信号作为输入。 每个输入级（23,33,43,53）也与公共节点（24,34,44,54）和选择晶体管（T4，T5，T6，T7）相关联。 每个选择晶体管（T4，T5，T6，T7）响应选择输入信号以将相应的公共节点（24,34,44,54）耦合到地。 这允许读出放大器（11）响应与相应输入级（23,33,43,53）相关联的位线对（20,21,30,31,40,41,50,51）上的数据信号 ）。
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公开(公告)号：US5982692A
公开(公告)日：1999-11-09
申请号：US905000
申请日：1997-08-01
CPC分类号： G11C7/18 , G11C7/1048 , G11C7/12
摘要： A method and apparatus is provided for implementing a memory cell array having a performance-improved critical read path using a boost amplifier configuration. The memory bit line is broken into small segments with a boost amplifier and the bit line is connected to the input of the amplifier. The output of the amplifier drives the global bit line. The amplifier is turned "on" during a "read" and turned "off" during a "write". During a read, one memory cell within one array segment is turned on. The memory cell drives the differential signal on to the local bit line pair. Also during a read, the boost amplifier which attaches to that local bit line is enabled. The boost amplifier amplifies the input signal (local bit line pair) and drives that signal on to the global bit line. Since the bit line is broken into small segments with boost amplifiers, there are many boost amplifiers attached on the global bit line. When enough signal is developed on the global bit line pair, the global sense amplifier is turned on. The bit line is thus quickly pulled to ground thereby significantly improving performance for the critical read path.
摘要翻译： 提供了一种用于实现具有使用升压放大器配置的性能改善的关键读取路径的存储单元阵列的方法和装置。 存储器位线用升压放大器分成小段，位线连接到放大器的输入。 放大器的输出驱动全局位线。 在“读取”期间，放大器“打开”并在“写入”期间关闭。 在读取期间，一个数组段内的一个存储单元被导通。 存储单元将差分信号驱动到本地位线对上。 此外，在读取期间，启用与本地位线相连的升压放大器。 升压放大器放大输入信号（局部位线对）并将该信号驱动到全局位线。 由于利用升压放大器将位线分解成小段，所以在全局位线上附加了许多升压放大器。 当在全局位线对上产生足够的信号时，全局读出放大器被打开。 因此，位线被快速拉到地，从而显着提高关键读路径的性能。
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公开(公告)号：US6046930A
公开(公告)日：2000-04-04
申请号：US144871
申请日：1998-09-01
IPC分类号： G11C8/16 , G11C11/412 , G11C11/419 , G11C11/00
CPC分类号： G11C11/419 , G11C11/412 , G11C8/16
摘要： A column (10) of a memory array includes a plurality of memory cells (11, 12) each having first and second independent access ports (T1, T2) and a cross-coupled memory latch (20). The first access port (T1) of each memory cell (11, 12) connects a first node (21) of the latch (20) to a first bit line (14), while the second access port (T2) of each memory cell connects a second node (22) of the latch (20) to a second bit line (15). A clearing arrangement (T7) is connected to the second bit line (15) for selectively coupling the second bit line to ground. A write driver is connected to the first bit line (14) for writing data to the memory cells (11, 12) in the form of single-ended signals. A memory cell is placed in a preset condition by simultaneously coupling the second node (22) to the second bit line (15) through the second access port (T2) and coupling the second bit line to ground through the clearing arrangement (T7). Once in the preset condition, data may be written to the cell by coupling the first bit line (14) to the first node (21) through the first access port (T1) and driving data to the first bit line.
摘要翻译： 存储器阵列的列（10）包括多个具有第一和第二独立访问端口（T1，T2）和交叉耦合存储器锁存器（20）的存储器单元（11,12）。 每个存储单元（11,12）的第一访问端口（T1）将锁存器（20）的第一节点（21）连接到第一位线（14），而每个存储单元的第二访问端口（T2） 将锁存器（20）的第二节点（22）连接到第二位线（15）。 清除装置（T7）连接到第二位线（15），用于选择性地将第二位线耦合到地。 写驱动器连接到第一位线（14），用于以单端信号的形式将数据写入存储单元（11,12）。 通过同时通过第二访问端口（T2）将第二节点（22）耦合到第二位线（15）并通过清除装置（T7）将第二位线耦合到地，将存储器单元置于预设状态。 一旦处于预设状态，通过将第一位线（14）通过第一访问端口（T1）耦合到第一节点（21）并将数据驱动到第一位线，可以将数据写入单元。
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4.发明授权Memory in a data processing system having uneven cell grouping on bitlines and method therefor 失效在位线上具有不均匀的单元分组的数据处理系统中的存储器及其方法
公开(公告)号：US5892725A
公开(公告)日：1999-04-06
申请号：US78248
申请日：1998-05-13
摘要： A memory and a method for communicating therewith are implemented, the memory having a plurality of memory cell groups. Each memory cell group contains a plurality of memory cells. Memory cell groups within each subset of a plurality of subsets of memory cell groups include the same predetermined number of memory cells. During a read operation, a local bitline associated with the memory cell group from which data is being read is coupled to a global bitline. Other local bitlines, associated with the memory cell groups not being accessed during the read are decoupled from the global bitlines. Following a read, the local and global bitlines are restored by a precharge operation.
摘要翻译： 实现与其通信的存储器和方法，该存储器具有多个存储单元组。 每个存储单元组包含多个存储单元。 存储器单元组的多个子集的每个子集内的存储单元组包括相同的预定数量的存储器单元。 在读取操作期间，与正在读取数据的存储器单元组相关联的本地位线被耦合到全局位线。 与读取期间未被访问的存储器单元组相关联的其他本地位线与全局位线分离。 读取后，通过预充电操作恢复本地和全局位线。
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公开(公告)号：US5892704A
公开(公告)日：1999-04-06
申请号：US52245
申请日：1998-03-31
CPC分类号： G11C8/08
摘要： A memory array of a plurality of memory cells accessed by either a single-ended wordline or a differential pair of wordlines emanating from a wordline decoder is improved by the inclusion of a sense amplifier circuit on the far end of the memory array from the wordline decoder, which operates to amplify the wordline signals.
摘要翻译： 通过在字线解码器的存储器阵列的远端包括读出放大器电路，可以通过从字线解码器发出的单端字线或字线的差分对访问的多个存储器单元的存储器阵列得到改善 ，其操作以放大字线信号。
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6.发明授权Memory in a data processing system having improved performance and method therefor 失效具有改进的性能和方法的数据处理系统中的存储器
公开(公告)号：US6058065A
公开(公告)日：2000-05-02
申请号：US82540
申请日：1998-05-21
CPC分类号： G11C7/18
摘要： A memory array is modified by segmenting the total length of a bitline into smaller bitline sections referred to as local bitlines. Included is an additional bitline into the array for every bitline that has been segmented. This new bitline is referred to as the global bitline. After segmentation, the array appears as several smaller sub-arrays; each sub-array has fewer cells per segmentation (local bitline) than the sum total of cells along the more traditional non-segmented bitline approach. These smaller sub-arrays (local bitline segmentations) are independent of one another and only one sub-array can be accessed per memory request (read/write). The reduced length and cell count per local bitline within each sub-array substantially reduces the total bitline capacitance (e.g., diffusion capacitance) discharged by a single memory cell during a read operation. Reducing bitline capacitance results in faster signal development and restore time on the bitline; thus, several smaller sub-arrays can be cycled much faster than a single large array.
摘要翻译： 通过将位线的总长度分割成称为本地位线的更小的位线部分来修改存储器阵列。 包括的是对于已经分段的每个位线，数组中都有一个位线。 这个新的位线被称为全局位线。 分割后，阵列显示为几个较小的子阵列; 每个子阵列比沿着更传统的非分段位线方法的细胞的总和小，每个分割（局部位线）具有更少的细胞。 这些较小的子阵列（本地位线分割）彼此独立，并且每个存储器请求（读/写）只能访问一个子阵列。 每个子阵列中的每个局部位线的减小的长度和单元计数基本上减少了在读取操作期间由单个存储器单元放电的总位线电容（例如，扩散电容）。 减少位线电容会导致更快的信号发展和位线恢复时间; 因此，几个较小的子阵列可以循环比单个大阵列快得多。
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公开(公告)号：US06002626A
公开(公告)日：1999-12-14
申请号：US904987
申请日：1997-08-01
摘要： A method and apparatus is provided for implementing a memory cell array having a performance-improved critical read path using a Domino boost amplifier configuration. The memory bit line is broken into small segments with a Domino boost amplifier and the bit line is connected to the input of the amplifier. The output of the amplifier drives the global bit line. The amplifier is turned "on" during a "read" and turned "off" during a "write". During a read, one memory cell within one array segment is turned on. The memory cell drives the differential signal on to the local bit line pair. Also during a read, the boost amplifier which attaches to that local bit line is enabled. The boost amplifier amplifies the input signal (local bit line pair) and drives that signal on to the global bit line. Since the bit line is broken into small segments with boost amplifiers, there are many boost amplifiers attached on the global bit line. When enough signal is developed on the global bit line pair, the other boost amplifiers which are attached to the global bit line will be turned on. The bit line is thus quickly pulled to ground thereby significantly improving performance for the critical read path.
摘要翻译： 提供了一种用于实现具有使用Domino升压放大器配置的性能改进的关键读取路径的存储单元阵列的方法和装置。 存储器位线用Domino升压放大器分成小段，位线连接到放大器的输入端。 放大器的输出驱动全局位线。 在“读取”期间，放大器“打开”并在“写入”期间关闭。 在读取期间，一个数组段内的一个存储单元被导通。 存储单元将差分信号驱动到本地位线对上。 此外，在读取期间，启用与本地位线相连的升压放大器。 升压放大器放大输入信号（局部位线对）并将该信号驱动到全局位线。 由于利用升压放大器将位线分解成小段，所以在全局位线上附加了许多升压放大器。 当在全局位线对上产生足够的信号时，附加到全局位线的其他升压放大器将被接通。 因此，位线被快速拉到地，从而显着提高关键读路径的性能。
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