公开(公告)号：US10056313B2

公开(公告)日：2018-08-21

申请号：US15576850

申请日：2016-01-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Siyang Liu ,  Ning Wang ,  Jiaxing Wei ,  Chao Liu ,  Weifeng Sun ,  Shengli Lu ,  Longxing Shi

IPC: H01L23/367 ,  H01L23/495 ,  H01L23/31 ,  H01L25/16 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/1306 ,  H01L2924/1426 ,  H01L2924/17738 ,  H01L2924/17747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A power module of a square flat pin-free packaging structure for suppressing the power module from being excessively high in local temperature. The power module includes an insulating resin, a driving chip, a plurality of power chips, and a plurality of metal electrode contacts. The driving chip, the power chips, and the metal electrode contacts are electrically connected through a metal lead according to a predetermined circuit. A plurality of metal heat dissipating disks used for heat dissipation of the power chips and a driving chip lead frame are disposed at the bottom of the insulating resin. A plurality of metal power chip lead frames are disposed on the metal heat dissipating disks, the power chips are disposed on the power chip lead frames, and the drain electrodes of the power chips are electrically connected to the metal heat dissipating disks.

公开(公告)号：US20140306266A1

公开(公告)日：2014-10-16

申请号：US14349632

申请日：2012-10-24

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng Sun ,  Siyang Liu ,  Jing Zhu ,  Qinsong Qian ,  Shen Xu ,  Shengli Lu ,  Longxing Shi

IPC: H01L29/739 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L29/7394 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0638 ,  H01L29/404

Abstract: A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

Abstract translation: 一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层 氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。 改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。