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    High-current N-type silicon-on-insulator lateral insulated-gate bipolar transistor
    2.
    发明授权
    High-current N-type silicon-on-insulator lateral insulated-gate bipolar transistor 有权
    大电流N型绝缘体上半导体绝缘栅双极晶体管

    公开(公告)号：US09159818B2

    公开(公告)日：2015-10-13

    申请号：US14349632

    申请日：2012-10-24

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weifeng Sun ,  Siyang Liu ,  Jing Zhu ,  Qinsong Qian ,  Shen Xu ,  Shengli Lu ,  Longxing Shi

    IPC: H01L27/24 ,  H01L29/739 ,  H01L29/40 ,  H01L27/12 ,  H01L29/06 ,  H01L27/06

    CPC classification number: H01L29/7394 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0638 ,  H01L29/404

    Abstract: A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

    Abstract translation: 一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层 氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。 改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

    HIGH-CURRENT N-TYPE SILICON-ON-INSULATOR LATERAL INSULATED-GATE BIPOLAR TRANSISTOR
    5.
    发明申请
    HIGH-CURRENT N-TYPE SILICON-ON-INSULATOR LATERAL INSULATED-GATE BIPOLAR TRANSISTOR 有权
    高电流N型绝缘子硅酸盐绝缘栅双极晶体管

    公开(公告)号：US20140306266A1

    公开(公告)日：2014-10-16

    申请号：US14349632

    申请日：2012-10-24

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weifeng Sun ,  Siyang Liu ,  Jing Zhu ,  Qinsong Qian ,  Shen Xu ,  Shengli Lu ,  Longxing Shi

    IPC: H01L29/739 ,  H01L27/12 ,  H01L27/06

    CPC classification number: H01L29/7394 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/0638 ,  H01L29/404

    Abstract: A high-current, N-type silicon-on-insulator lateral insulated-gate bipolar transistor, including: a P-type substrate, a buried-oxide layer disposed on the P-type substrate, an N-type epitaxial layer disposed on the oxide layer, and an N-type buffer trap region. A P-type body region and an N-type central buffer trap region are disposed inside the N-type epitaxial layer; a P-type drain region is disposed in the buffer trap region; N-type source regions and a P-type body contact region are disposed in the P-type body region; an N-type base region and a P-type emitter region are disposed in the buffer trap region; gate and field oxide layers are disposed on the N-type epitaxial layer; polycrystalline silicon gates are disposed on the gate oxide layers; and a passivation layer and metal layers are disposed on the surface of the symmetrical transistor. P-type emitter region output and current density are improved without increasing the area of the transistor.

    Abstract translation: 一种高电流，N型绝缘体上的横向绝缘栅双极晶体管，包括：P型衬底，设置在P型衬底上的掩埋氧化物层，设置在P型衬底上的N型外延层 氧化物层和N型缓冲阱捕获区。 P型体区域和N型中央缓冲区捕获区域设置在N型外延层内部; P型漏极区域设置在缓冲陷阱区域中; N型源极区域和P型体接触区域设置在P型体区域中; N型基极区域和P型发射极区域设置在缓冲陷阱区域中; 栅极和场氧化物层设置在N型外延层上; 多晶硅栅极设置在栅极氧化物层上; 并且钝化层和金属层设置在对称晶体管的表面上。 改善P型发射极区域的输出和电流密度，而不增加晶体管的面积。

    Synchronous rectification control system and method for quasi-resonant flyback converter
    6.
    发明授权
    Synchronous rectification control system and method for quasi-resonant flyback converter 有权

    公开(公告)号：US11984813B2

    公开(公告)日：2024-05-14

    申请号：US17435789

    申请日：2020-05-15

    Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

    Inventor： Shen Xu ,  Siyu Zhao ,  Congming Qi ,  Sen Zhang ,  Xiaoyu Shi ,  Weifeng Sun ,  Longxing Shi

    IPC: H02M3/335 ,  H02M1/00 ,  H02M1/38

    CPC classification number: H02M3/33592 ,  H02M1/0058 ,  H02M1/38

    Abstract: A synchronous rectification control system and method for a quasi-resonant flyback converter are provided. The control system includes a switching transistor voltage sampling circuit configured to sample an output terminal voltage of the switching transistor to obtain a sampled voltage of the switching transistor; a sampling calculation module configured to obtain a dead-time based on the sampled voltage of the switching transistor and a preset relationship, the preset relationship being a correspondence between the duration of the sampled voltage of the switching transistor being below a first preset value and the dead-time during an on-time of a switching cycle of the switching transistor, the dead-time being a time from when the switching transistor is turned off to when the synchronous rectification transistor is turned on; and a control module configured to receive the dead-time and control switching of the synchronous rectification transistor based on the dead-time.

    TRANSVERSE ULTRA-THIN INSULATED GATE BIPOLAR TRANSISTOR HAVING HIGH CURRENT DENSITY
    7.
    发明申请
    TRANSVERSE ULTRA-THIN INSULATED GATE BIPOLAR TRANSISTOR HAVING HIGH CURRENT DENSITY 有权
    具有高电流密度的横向超薄绝缘栅双极晶体管

    公开(公告)号：US20150270377A1

    公开(公告)日：2015-09-24

    申请号：US14439715

    申请日：2012-12-27

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weifeng Sun ,  Jing Zhu ,  Shen Xu ,  Qinsong Qian ,  Siyang Liu ,  Shengli Lu ,  Longxing Shi

    IPC: H01L29/739 ,  H01L23/528 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/49

    CPC classification number: H01L29/7394 ,  H01L23/528 ,  H01L29/0611 ,  H01L29/0696 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/1008 ,  H01L29/4916 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.

    Abstract translation: 具有电流密度的横向超薄绝缘栅双极晶体管包括：P基板，其中P基板在其上设置有掩埋氧化物层，所述掩埋氧化物层在其上设置有N外延层，提供N外延层 在其中具有N阱区域和P基极区域，P基极区域中设置有第一P接触区域和N源极区域，N阱区域中设置有N个缓冲区域，N阱区域设置有 在其上的场氧化物层，N缓冲区在其中设置有P漏极区，N外延层中设置有包括P环状基极区的P基区阵列，P基区阵列位于N阱之间 区域和P基区域中，P环状基部区域设置有第二P接触区域和N环状源极区域，第二P接触区域位于N环状源极区域中。 本发明大大增加了横向超薄绝缘栅双极晶体管的电流密度，从而显着提高了智能功率模块的性能。

    Multi-phase high-precision current sharing control method applied to constant on-time control
    8.
    发明授权
    Multi-phase high-precision current sharing control method applied to constant on-time control 有权

    公开(公告)号：US12046990B1

    公开(公告)日：2024-07-23

    申请号：US18641384

    申请日：2024-04-21

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Shen Xu ,  Haiqing Zhang ,  Yujie Liu ,  Ruizhi Wang ,  Yuan Gao ,  Yongjia Li ,  Weifeng Sun ,  Longxing Shi

    IPC: H02M1/08 ,  H02M1/00 ,  H02M3/158

    CPC classification number: H02M1/082 ,  H02M1/0025 ,  H02M3/1586

    Abstract: A multi-phase high-precision current sharing control method applied to constant on-time control is provided, wherein a current difference between continuously sampled current of each line and mean current is processed by a PI compensation module and a low-pass filter module to obtain on-time regulation data. A high bit of the regulation data controls the value of counter reference Vref in an on-time control module, and a low bit controls the length of an enabled delay line in a delay line module. The counter timing control of the on-time control module is combined with the delay line timing control of the delay line module to improve the control precision of a DPWM. The method takes COT control of a Buck converter as a typical application. Compared with a multi-phase COT controller without a current-sharing mechanism, the method can improve the stability and reliability of the system.

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