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31.发明授权Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processor 有权用于处理无序多问题多链处理器中条件码修改器的方法公开(公告)号：US07065635B1
公开(公告)日：2006-06-20
申请号：US10738576
申请日：2003-12-17
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/30094 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A technique for handling a condition code modifying instruction in an out-of-order multi-stranded processor involves providing a condition code architectural register file for each strand, providing a condition code working register file, and assigning condition code architectural register file identification information (CARF_ID) and condition code working register file identification information (CWRF_ID) to the condition code modifying instruction. CARF_ID is used to index a location in a condition code rename table to which the CWRF_ID is stored. Thereafter, upon an exception-free execution of the condition code modifying instruction, a result of the execution is copied from the condition code working register file to the condition code architectural register file dependent on CARF_ID, CWRF_ID, register type information, and strand identification information.
摘要翻译： 一种用于处理无序多股处理器中的条件代码修改指令的技术包括为每条链提供条件代码体系结构寄存器文件，提供条件代码工作寄存器文件，以及分配条件码架构寄存器文件识别信息（ CARF_ID）和条件代码工作寄存器文件识别信息（CWRF_ID）到条件代码修改指令。 CARF_ID用于索引存储CWRF_ID的条件代码重命名表中的位置。 此后，在条件代码修改指令的无异常执行时，执行结果从条件代码工作寄存器文件复制到依赖于CARF_ID，CWRF_ID，寄存器类型信息和链标识信息的条件代码架构寄存器文件 。
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公开(公告)号：US06820086B1
公开(公告)日：2004-11-16
申请号：US09336046
申请日：1999-06-18
IPC分类号： G06F700
CPC分类号： G06F17/30958 , Y10S707/99931
摘要： A linked list structure in a computing system includes a first entry and additional entries. Each additional entry includes a link reference to a prior entry in the linked list. The link reference for each additional entry all are stored within a content addressable memory. Each additional entry is accessible by performing a content search using the link reference to the prior entry. The linked list is traversed by accessing the first entry in the linked list. A second entry in the linked list is accessed by searching the content addressable memory with an index of the first entry. A third entry in the linked list is accessed by searching the content addressable memory with an index of the second entry.
摘要翻译： 计算系统中的链表结构包括第一条目和附加条目。 每个附加条目包括对链接列表中先前条目的链接引用。 每个附加条目的链接引用全部存储在内容可寻址存储器中。 通过使用前一条目的链接引用执行内容搜索，可以访问每个附加条目。 通过访问链表中的第一个条目遍历链表。 通过用第一条目的索引搜索内容可寻址存储器来访问链表中的第二条目。 通过用第二条目的索引搜索内容可寻址存储器来访问链表中的第三条目。
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公开(公告)号：US5995967A
公开(公告)日：1999-11-30
申请号：US734003
申请日：1996-10-18
CPC分类号： G06F17/30958 , Y10S707/99931
摘要： A linked list structure in a computing system includes a first entry and additional entries. Each additional entry includes a link reference to a prior entry in the linked list. The link reference for each additional entry all are stored within a content addressable memory. Each additional entry is accessible by performing a content search using the link reference to the prior entry. The linked list is traversed by accessing the first entry in the linked list. A second entry in the linked list is accessed by searching the content addressable memory with an index of the first entry. A third entry in the linked list is accessed by searching the content addressable memory with an index of the second entry.
摘要翻译： 计算系统中的链表结构包括第一条目和附加条目。 每个附加条目包括对链接列表中先前条目的链接引用。 每个附加条目的链接引用全部存储在内容可寻址存储器中。 通过使用前一条目的链接引用执行内容搜索，可以访问每个附加条目。 通过访问链表中的第一个条目遍历链表。 通过用第一条目的索引搜索内容可寻址存储器来访问链表中的第二条目。 通过用第二条目的索引搜索内容可寻址存储器来访问链表中的第三条目。
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34.发明授权
公开(公告)号：US5696939A
公开(公告)日：1997-12-09
申请号：US536534
申请日：1995-09-29
申请人： Sorin Iacobovici , Dean A. Mulla
发明人： Sorin Iacobovici , Dean A. Mulla
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30087 , G06F9/3885 , G06F9/52
摘要： A simplified semaphore method and apparatus for simultaneous execution of multiple semaphore instructions and for enforcement of necessary ordering. A central processing unit having an instruction pipeline is coupled with a data cache arrangement including a semaphore buffer, a data cache, and the semaphore execution unit. An initial semaphore instruction having one or more operands and a semaphore address are transmitted from the instruction pipeline to the semaphore buffer, which in turn are transmitted from the semaphore buffer to the semaphore execution unit. The semaphore address of the initial semaphore instruction is transmitted from the instruction pipeline to the data cache to retrieve initial semaphore data stored within the data cache at a location in a data line of the data cache as identified by the semaphore address. The semaphore instruction is executed within the semaphore execution unit by operating upon the initial semaphore data and the one or more semaphore operands so as to produce processed semaphore data, which is then stored within the data cache. Since the semaphore buffer provides for entries of multiple semaphore instructions, the semaphore buffer initiates simultaneous execution of multiple semaphore instructions, as needed.
摘要翻译： 用于同时执行多个信号量指令并执行必要排序的简化信号量方法和装置。 具有指令流水线的中央处理单元与包括信号量缓冲器，数据高速缓存和信号量执行单元的数据高速缓存装置耦合。 具有一个或多个操作数和信号量地址的初始信号量指令从指令流水线发送到信号量缓冲器，信号量缓冲器又从信号量缓冲器发送到信号量执行单元。 初始信号量指令的信号量地址从指令流水线发送到数据高速缓存，以在信号量地址识别的数据高速缓存的数据行中的位置检索存储在数据高速缓存内的初始信号量数据。 信号量指令通过操作初始信号量数据和一个或多个信号量操作数在信号量执行单元内执行，以产生处理后的信号量数据，然后存储在数据高速缓存中。 由于信号量缓冲器提供多个信号量指令的条目，因此信号量缓冲区根据需要启动多个信号量指令的同时执行。
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35.发明授权Processor with in-system emulation circuitry which uses the same group of terminals to output program counter bits 失效具有系统内仿真电路的处理器，其使用相同组的终端来输出程序计数器位
公开(公告)号：US5493723A
公开(公告)日：1996-02-20
申请号：US330222
申请日：1994-10-27
申请人： Motti Beck , Ran Talmudi , Sorin Iacobovici
发明人： Motti Beck , Ran Talmudi , Sorin Iacobovici
CPC分类号： G06F11/3648
摘要： A processor emulation system for testing processor operation. First and second identical microprocessors are used together with a target system which includes the main memory. One microprocessor performs an in-system emulation (ISE) function by operating in lock step with the second processor which functions as the master processor. A mode control signal is used to switch the microprocessors between a normal operating mode and an ISE mode. Normal microprocessor signals are outputted on predetermined terminals for the processor in the normal operating mode and the parallel contents of the processor program counter are outputted on the same predetermined terminals when the microprocessor is in the ISE mode. The master processor provides output signals to the target system, with the ISE processor and the master processor both receiving signals from the target system. Operation of the master processor can be ascertained by monitoring the program counter output of the ISE processor.
摘要翻译： 用于测试处理器操作的处理器仿真系统。 第一和第二相同的微处理器与包括主存储器的目标系统一起使用。 一个微处理器通过与用作主处理器的第二处理器在锁定步骤中操作来执行系统内仿真（ISE）功能。 模式控制信号用于在正常操作模式和ISE模式之间切换微处理器。 正常的微处理器信号在正常操作模式下为处理器的预定端子输出，并且当微处理器处于ISE模式时，处理器程序计数器的并行内容在相同的预定端子上被输出。 主处理器向目标系统提供输出信号，ISE处理器和主处理器都接收来自目标系统的信号。 可以通过监视ISE处理器的程序计数器输出来确定主处理器的操作。
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