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公开(公告)号：US06820086B1
公开(公告)日：2004-11-16
申请号：US09336046
申请日：1999-06-18
IPC分类号： G06F700
CPC分类号： G06F17/30958 , Y10S707/99931
摘要： A linked list structure in a computing system includes a first entry and additional entries. Each additional entry includes a link reference to a prior entry in the linked list. The link reference for each additional entry all are stored within a content addressable memory. Each additional entry is accessible by performing a content search using the link reference to the prior entry. The linked list is traversed by accessing the first entry in the linked list. A second entry in the linked list is accessed by searching the content addressable memory with an index of the first entry. A third entry in the linked list is accessed by searching the content addressable memory with an index of the second entry.
摘要翻译： 计算系统中的链表结构包括第一条目和附加条目。 每个附加条目包括对链接列表中先前条目的链接引用。 每个附加条目的链接引用全部存储在内容可寻址存储器中。 通过使用前一条目的链接引用执行内容搜索，可以访问每个附加条目。 通过访问链表中的第一个条目遍历链表。 通过用第一条目的索引搜索内容可寻址存储器来访问链表中的第二条目。 通过用第二条目的索引搜索内容可寻址存储器来访问链表中的第三条目。
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公开(公告)号：US5995967A
公开(公告)日：1999-11-30
申请号：US734003
申请日：1996-10-18
CPC分类号： G06F17/30958 , Y10S707/99931
摘要： A linked list structure in a computing system includes a first entry and additional entries. Each additional entry includes a link reference to a prior entry in the linked list. The link reference for each additional entry all are stored within a content addressable memory. Each additional entry is accessible by performing a content search using the link reference to the prior entry. The linked list is traversed by accessing the first entry in the linked list. A second entry in the linked list is accessed by searching the content addressable memory with an index of the first entry. A third entry in the linked list is accessed by searching the content addressable memory with an index of the second entry.
摘要翻译： 计算系统中的链表结构包括第一条目和附加条目。 每个附加条目包括对链接列表中先前条目的链接引用。 每个附加条目的链接引用全部存储在内容可寻址存储器中。 通过使用前一条目的链接引用执行内容搜索，可以访问每个附加条目。 通过访问链表中的第一个条目遍历链表。 通过用第一条目的索引搜索内容可寻址存储器来访问链表中的第二条目。 通过用第二条目的索引搜索内容可寻址存储器来访问链表中的第三条目。
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公开(公告)号：US07555692B1
公开(公告)日：2009-06-30
申请号：US11135982
申请日：2005-05-24
申请人： Sorin Iacobovici
发明人： Sorin Iacobovici
CPC分类号： G06F9/3001 , G06F9/3859 , G06F9/3865 , G06F9/3887 , G06F11/0721 , G06F11/0751 , G06F11/104 , G06F11/14
摘要： A processor that protects an execution pipeline includes a residue-based error detection infrastructure including a first logic for computing a first residue of a result of an executed instruction instance, and a second logic for computing a second residue of the result. The second logic applies arithmetic operations of the executed instruction instance to residues of operands of the instruction instance. The execution pipeline includes registers and one or more arithmetic execution units. A method of protecting an execution pipeline includes performing one or more operations of an instruction instance on residues of operands of the instruction instance, computing a first residue of a result of the operations on the operand residues, computing a second residue from a result of executing the instruction instance, and checking the first residue against the second residue to determine whether errors were introduced while the instruction instance was resident in the execution pipeline.
摘要翻译： 保护执行流水线的处理器包括基于残差的错误检测基础设施，包括用于计算执行的指令实例的结果的第一个残差的第一逻辑，以及用于计算结果的第二个残差的第二逻辑。 第二逻辑将执行的指令实例的算术运算应用于指令实例的操作数的残差。 执行流水线包括寄存器和一个或多个算术执行单元。 一种保护执行流水线的方法包括对指令实例的操作数的残差执行指令实例的一个或多个操作，计算操作数残差上的操作结果的第一个残差，从执行结果计算第二个残差 指令实例，并根据第二个残差检查第一个残差，以确定在指令实例驻留在执行管道中时是否引入了错误。
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4.发明授权Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction stream 有权方法和系统，用于使用相同的寄存器组来处理指令流中的单精度和双精度浮点指令公开(公告)号：US07191316B2
公开(公告)日：2007-03-13
申请号：US10353662
申请日：2003-01-29
CPC分类号： G06F9/3836 , G06F9/30014 , G06F9/30101 , G06F9/384 , G06F9/3857
摘要： A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.
摘要翻译： 提供了一种用于处理多个单精度浮点指令和多个双精度浮点指令的系统，它们都对同一组寄存器进行索引。 该系统包括解码单元，其被配置为在取出组中解码，停止和转发多个单精度和至少一个双精度浮点指令中的至少一个。 所述解码单元包括第一计数器，所述第一计数器被布置为针对沿管线转发的所述多个单精度浮点指令中的每一者递增; 第二计数器，被布置为针对沿着流水线转发的多个双精度浮点指令中的每一个递增; 第一屏蔽寄存器和第二掩码寄存器。 通过转发的每个单精度浮点指令来更新第一个掩码寄存器，并且通过转发的每个双精度浮点指令更新第二个掩码寄存器。
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5.发明授权Method and apparatus for processing a complex instruction for execution and retirement 有权处理执行和退休的复杂指令的方法和装置公开(公告)号：US07124284B2
公开(公告)日：2006-10-17
申请号：US10337056
申请日：2003-01-06
CPC分类号： G06F9/3017 , G06F9/3013 , G06F9/3836 , G06F9/384 , G06F9/3851 , G06F9/3857
摘要： A method and apparatus to determine readiness of a complex instruction for retirement includes decoding a complex instruction into a plurality of helper instructions; executing the plurality of helper instructions using an execution unit; indicating the plurality of helper instructions that are alive using a live instruction register; and maintaining a complex instruction identification for the complex instruction using a complex instruction identification register.
摘要翻译： 确定用于退休的复杂指令的准备状态的方法和装置包括将复杂指令解码为多个辅助指令; 使用执行单元执行所述多个帮助指令; 指示使用实时指令寄存器存在的多个辅助指令; 并使用复杂指令识别寄存器维持复杂指令的复杂指令识别。
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6.发明授权Method and apparatus for protecting a state associated with a memory structure 有权用于保护与存储器结构相关联的状态的方法和装置公开(公告)号：US07043609B2
公开(公告)日：2006-05-09
申请号：US10357643
申请日：2003-02-03
申请人： Victor Melamed , Sorin Iacobovici
发明人： Victor Melamed , Sorin Iacobovici
IPC分类号： G06F12/08
CPC分类号： G06F11/141 , G06F11/0724 , G06F11/0793 , G06F11/1064 , G06F12/0831
摘要： A method for protecting reliability of data associated with a data array is provided. The method initiates with defining state information associated with the data array. Then, crucial state information is identified from the state information. Next, a copy of the crucial state information is generated. Then, the state information and the copy of the crucial state information are protected. Next, a worst case state associated with non-crucial information is defined. In response to detecting an error associated with the non-crucial information, the method includes defaulting to the worst case state. A computer readable media and a shared memory multiprocessor chip are also provided.
摘要翻译： 提供了一种用于保护与数据阵列相关联的数据的可靠性的方法。 该方法通过定义与数据阵列相关联的状态信息来启动。 然后，从状态信息中识别关键的状态信息。 接下来，生成关键状态信息的副本。 然后，保护状态信息和关键状态信息的副本。 接下来，定义与非关键信息相关联的最坏情况状态。 响应于检测到与非关键信息相关联的错误，该方法包括默认为最坏情况状态。 还提供了计算机可读介质和共享存储器多处理器芯片。
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7.发明授权Cache arrangement including coalescing buffer queue for non-cacheable data 失效缓存排列包括用于非可缓存数据的合并缓冲区队列
公开(公告)号：US5664148A
公开(公告)日：1997-09-02
申请号：US515551
申请日：1995-08-17
申请人： Dean Mulla , Sorin Iacobovici
发明人： Dean Mulla , Sorin Iacobovici
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： An apparatus including a cache subsystem arrangement for efficient management of input/output operations and of memory shared by processors in a multiprocessor system. The apparatus includes a central processing unit, an input/output device such as a network device or a display device for example, and the cache arrangement, which includes a coalescing buffer coupled with the data processing unit for receiving non-cacheable data from the processing unit. The non-cacheable data is combined in the coalescing buffer into non-cacheable data blocks. A system bus is coupled with the buffer and the input/output device for storing the non-cacheable data blocks to the input/output device. By combining the non-cacheable data before storage to the input/output device, the coalescing buffer provides higher performance in the multiprocessor system, since fewer bus transactions are issued for serial store operations and more stores can complete in a given amount of time than if they were issued singly on the bus. This is particularly advantageous in the multiprocessing system since multiple processors must compete for limited bus transaction bandwidth.
摘要翻译： 一种包括用于有效管理输入/输出操作和由多处理器系统中的处理器共享的存储器的高速缓存子系统装置的装置。 该装置包括中央处理单元，例如网络设备或显示设备的输入/输出设备，以及高速缓存布置，其包括与数据处理单元耦合的聚结缓冲器，用于从处理接收不可缓存的数据 单元。 非可缓存数据在合并缓冲器中组合成非可缓存数据块。 系统总线与缓冲器和输入/输出设备耦合，用于将不可缓存的数据块存储到输入/输出设备。 通过将存储前的不可缓存数据与输入/输出设备相结合，合并缓冲区在多处理器系统中提供更高的性能，因为为串行存储操作发出更少的总线事务，并且更多的存储可以在给定的时间量内完成，如 他们在公共汽车上单独发行。 这在多处理系统中是特别有利的，因为多个处理器必须竞争有限的总线事务带宽。
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公开(公告)号：US20150370636A1
公开(公告)日：2015-12-24
申请号：US14308107
申请日：2014-06-18
申请人： Guillem Sole , Roger Espasa , Sorin Iacobovici , Brian Hickmann , Wei Wu , Thomas Fletcher
发明人： Guillem Sole , Roger Espasa , Sorin Iacobovici , Brian Hickmann , Wei Wu , Thomas Fletcher
CPC分类号： H03M13/09 , G06F11/1012 , H03M13/17 , H03M13/19 , H03M13/29
摘要： Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome.
摘要翻译： 公开了用于连续位错检测和校正的发明的实施例。 在一个实施例中，一种装置包括存储结构，第二存储结构，奇偶校验器，纠错码（ECC）检查器和纠错器。 第一存储结构是存储多个数据值，多个奇偶校验值和多个ECC值，每个奇偶校验值对应于多个数据值之一，每个奇偶校验值的第一位对应于第一 对应数据值的多个部分中的相应数据值的多个部分中的第一部分与相应数据值的多个部分中的第二部分进行交织，其中每个奇偶校验值的第二位对应于 相应数据值的多个部分中的第二个，每个ECC值对应于多个数据值之一。 奇偶校验器使用与数据值相对应的奇偶校验值来检测存储在第一存储结构中的数据值中的奇偶校验错误。 ECC检查器是产生综合征。 错误校正器是使用综合征来检测和纠正数据值中的连续位错误。
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9.发明授权Handling register dependencies between instructions specifying different width registers 有权在指定不同宽度寄存器的指令之间处理寄存器依赖关系公开(公告)号：US07340590B1
公开(公告)日：2008-03-04
申请号：US10734763
申请日：2003-12-11
IPC分类号： G06F9/312
CPC分类号： G06F9/3836 , G06F9/30036 , G06F9/30112 , G06F9/3017 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： The present application describes a method and a processor for handling register dependency conflicts between lesser and greater width instructions, colloquially referred to as “evil twins.” If there is a register dependency between a greater width producer instruction and a lesser width consumer instruction, a greater width source register is substituted for the source register specified by the lesser width producer. If there is a register dependency between a lesser width producer instruction and a greater width producer instruction, the greater width consumer instruction is replaced by multiple helper instructions. One or more of the helper instructions merge lesser width registers aliased onto the source registers specified by the greater width consumer instruction, into temporary registers. Another helper instruction executes the greater width consumer instruction using the temporary registers instead of the original source registers.
摘要翻译： 本申请描述了一种用于处理较小和较大宽度指令之间的寄存器依赖性冲突的方法和处理器，通俗地称为“邪恶的双胞胎”。 如果在较大宽度的生产者指令和较小宽度的使用者指令之间存在寄存器依赖关系，则较大的宽度源寄存器将替代较小宽度生产者指定的源寄存器。 如果较小宽度生成器指令和较大宽度生成器指令之间存在寄存器依赖关系，则较大宽度的消费者指令将被多个辅助指令替换。 一个或多个辅助指令将较小宽度寄存器的别名合并到由较大宽度的消费者指令指定的源寄存器中，并入临时寄存器。 另一个帮助指令使用临时寄存器而不是原始源寄存器来执行更大的宽度使用者指令。
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10.发明授权Vector technique for addressing helper instruction groups associated with complex instructions 有权用于寻址与复杂指令相关联的辅助指令组的向量技术公开(公告)号：US07219218B2
公开(公告)日：2007-05-15
申请号：US10403530
申请日：2003-03-31
CPC分类号： G06F9/3017 , G06F9/30145 , G06F9/3822 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calculations or the like) are expanded into helper instructions before execution (e.g., in the integer, floating point, graphics and memory units or the like). Such instructions are treated as complex instructions. The functionality of a complex instruction is shared among multiple helpers so that by executing the helpers representing the complex instruction, the functionality of complex instruction is achieved. The expansion of complex instructions into helper instructions reduces the amount of hardware and complexity involved in supporting these individual complex instructions in various units in the processor.
摘要翻译： 本申请描述了一种用于在减少处理器中执行所需的逻辑的同时执行指令的方法和系统。 指令（例如，原子，整数乘法，整数除法，整数寄存器移动，图形，浮点计算等）在执行之前扩展为辅助指令（例如，在整数，浮点，图形和存储单元或 类似）。 这些说明被视为复杂的说明。 复杂指令的功能在多个助手之间共享，因此通过执行表示复杂指令的助手，实现了复杂指令的功能。 将复杂指令扩展到辅助指令中减少了处理器中各种单元支持这些单独复杂指令所涉及的硬件和复杂性的量。
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