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公开(公告)号：US06204710B1
公开(公告)日：2001-03-20
申请号：US09102730
申请日：1998-06-22
IPC分类号： H03K513
CPC分类号： H03K5/133 , H03K2005/00058 , H03K2005/00084
摘要： A precision trim circuit for a tuneable delay line is provided. The precision trim circuit provides delays greater than the base delay of the tuneable delay line. By using larger delays than conventional trim circuits, the precision trim circuit of the present invention can use components that react to process and environmental variations in the same manner as the components of the tuneable delay line. Specifically, one embodiment of the precision trim circuit comprises a first delay element providing a delay greater than or equal to the base delay of the tuneable delay line. The precision trim circuit also comprises a second delay element providing a greater delay than the first delay element. A multiplexer coupled to the first delay element and the second delay element is used to select the amount of delay provided by the precision trim circuit. Other embodiments include additional delay elements providing varying delay values.
摘要翻译： 提供了一种用于可调延迟线的精密微调电路。 精密微调电路提供大于可调延迟线的基本延迟的延迟。 通过使用比传统的微调电路更大的延迟，本发明的精密微调电路可以以与可调延迟线的组件相同的方式使用对处理和环境变化做出反应的组件。 具体地，精密微调电路的一个实施例包括提供大于或等于可调延迟线的基本延迟的延迟的第一延迟元件。 精密微调电路还包括提供比第一延迟元件更大的延迟的第二延迟元件。 耦合到第一延迟元件和第二延迟元件的多路复用器用于选择由精密调整电路提供的延迟量。 其他实施例包括提供可变延迟值的附加延迟元件。
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公开(公告)号：US06744274B1
公开(公告)日：2004-06-01
申请号：US10206872
申请日：2002-07-26
IPC分类号： H03K19177
CPC分类号： G06F11/2733 , G01R31/31724 , G01R31/318516 , G06F17/5054 , H03K19/17704 , H03K19/17736 , H03K19/17764
摘要： A programmable logic core (PLC) can be integrated into custom ICS such as ASICs and SOCs. An example PLC for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an array of configurable ALUs, an Application Circuit Interface (ACI) that provides signal interface between the MSA and application circuitry, and a PLC Adapter that initiates and loads the PLC configuration data and interfaces.
摘要翻译： 可编程逻辑内核（PLC）可以集成到定制ICS中，如ASIC和SOC。 用于集成到定制IC中的示例PLC包括由可配置ALU阵列组成的多尺度阵列（MSA），在MSA和应用电路之间提供信号接口的应用电路接口（ACI）以及启动的可编程控制器适配器 并加载PLC配置数据和接口。
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3.发明授权
公开(公告)号：US5148516A
公开(公告)日：1992-09-15
申请号：US238235
申请日：1988-08-30
申请人： Joseph H. Hassoun
发明人： Joseph H. Hassoun
CPC分类号： G09G5/222
摘要： A CRT computer terminal is presented. The need for a master processor is eliminated by designing a CRT controller to initialize a slave processor. The slave processor accesses a random access memory (RAM) in which is stored instructions which the processor executes. Upon initialization of the computer terminal, the CRT controller reads instructions to be executed by the slave processor from a non-volatile read-only memory (ROM). The instructions are transferred from the CRT controller to the slave processor. The slave processor stores the instructions in the random access memory. Each instruction, at the proper time, may then retrieved and executed by the slave processor.
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公开(公告)号：US07317773B2
公开(公告)日：2008-01-08
申请号：US10888203
申请日：2004-07-09
IPC分类号： H04L7/00
CPC分类号： H04J3/047
摘要： Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.
摘要翻译： 用于使逻辑路径上的数据传输的吞吐率加倍的方法和装置包括提供交替地接收待发送的数据流的连续位的两个锁存器和具有由两个分离的时钟交替计时的数据传输路径的多路复用器 基本相差180度。
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公开(公告)号：US06777980B2
公开(公告)日：2004-08-17
申请号：US10342574
申请日：2003-01-15
IPC分类号： H03K19173
CPC分类号： H04J3/047
摘要： Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.
摘要翻译： 用于使逻辑路径上的数据传输的吞吐率加倍的方法和装置包括提供交替地接收待发送的数据流的连续位的两个锁存器和具有由两个分离的时钟交替计时的数据传输路径的多路复用器 基本相差180度。
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公开(公告)号：US06487648B1
公开(公告)日：2002-11-26
申请号：US09464215
申请日：1999-12-15
申请人： Joseph H. Hassoun
发明人： Joseph H. Hassoun
IPC分类号： G06F1200
CPC分类号： G06F13/1689
摘要： A programmable logic device (PLD) implementing an SDRAM controller is provided. The configurable logic of the PLD forms an interface between the system and the SDRAM, as well as a state machine to operate the controller and the interface. In this manner, many functions of the SDRAM controller can be selectively controlled and easily changed by reprogramming the PLD. The configurable logic of the PLD also forms a state machine to operate the controller and the interface. In accordance with the present invention, dedicated circuits of the PLD optimize performance of the SDRAM controller. These dedicated circuits include two delay locked loops (DLLs) which eliminate skew between the system clock, a global clock in the PLD, and the SDRAM clock.
摘要翻译： 提供了一种实现SDRAM控制器的可编程逻辑器件（PLD）。 PLD的可配置逻辑形成系统和SDRAM之间的接口，以及用于操作控制器和接口的状态机。 以这种方式，可以通过重新编程PLD来选择性地控制和容易地改变SDRAM控制器的许多功能。 PLD的可配置逻辑还形成一个状态机来操作控制器和接口。 根据本发明，PLD的专用电路优化了SDRAM控制器的性能。 这些专用电路包括两个延迟锁定环（DLL），可消除系统时钟，PLD中的全局时钟与SDRAM时钟之间的偏差。
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公开(公告)号：US06289068B1
公开(公告)日：2001-09-11
申请号：US09102740
申请日：1998-06-22
IPC分类号： H03D324
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： A delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal. The delay line is coupled to a reference input terminal of the delay lock loop and generates a delayed clock signal that is provided to the clock phase shifter. The clock phase shifter generates one or more phase-shifted clock signals from the delayed clock signal. An output generator coupled to the delay line, the clock phase shifter, and an output terminal of the delay lock loop provides either the delayed clock signal or one of the phase-shifted clock signals as an output clock signal of the delayed lock loop. The propagation delay of the delay line is set to synchronize the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop. A phase detector compares the reference clock signal and the skewed clock signal to determine the appropriate propagation delay for the delay line.
摘要翻译： 延迟锁定环使用具有延迟线的时钟移相器来使参考时钟信号与偏斜时钟信号同步。 延迟线耦合到延迟锁定环的参考输入端，并产生提供给时钟移相器的延迟时钟信号。 时钟移相器从延迟的时钟信号产生一个或多个相移时钟信号。 耦合到延迟线的输出发生器，时钟移相器和延迟锁定环路的输出端子提供延迟时钟信号或相移时钟信号中的一个作为延迟锁定环路的输出时钟信号。 延迟线的传播延迟被设置为使参考时钟信号与延迟锁定环路的反馈输入端上接收到的偏斜时钟信号同步。 相位检测器比较参考时钟信号和偏斜时钟信号，以确定延迟线的适当传播延迟。
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公开(公告)号：US6061418A
公开(公告)日：2000-05-09
申请号：US103172
申请日：1998-06-22
申请人： Joseph H. Hassoun
发明人： Joseph H. Hassoun
CPC分类号： H03K21/10
摘要： A variable clock divider circuit is provided. The variable clock divider circuit receives an input clock signal and generates an output clock signal having an output clock frequency that is less than the input clock frequency of the input clock signal. In one embodiment, a controller generates a rising-edge control signal and a falling-edge control signal. An output generator drives rising edges on the output clock signal in response to active edges on the rising-edge control signal. Conversely, the output generator drives falling edges on the output clock signal in response to active edges on the falling-edge control signal. The frequency of the rising-edge control signal and the frequency of the falling-edge control signal are variable. Common settings for the frequency of the rising-edge control signal and the falling-edge control signal include the frequency of the input clock signal divided by an integer.
摘要翻译： 提供可变时钟分频电路。 可变时钟分频器电路接收输入时钟信号并产生具有小于输入时钟信号的输入时钟频率的输出时钟频率的输出时钟信号。 在一个实施例中，控制器产生上升沿控制信号和下降沿控制信号。 输出发生器响应于上升沿控制信号上的有效边沿驱动输出时钟信号上的上升沿。 相反，输出发生器响应于下降沿控制信号上的有效边沿驱动输出时钟信号的下降沿。 上升沿控制信号的频率和下降沿控制信号的频率是可变的。 上升沿控制信号和下降沿控制信号的频率的共同设置包括输入时钟信号的频率除以整数。
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公开(公告)号：US06820086B1
公开(公告)日：2004-11-16
申请号：US09336046
申请日：1999-06-18
IPC分类号： G06F700
CPC分类号： G06F17/30958 , Y10S707/99931
摘要： A linked list structure in a computing system includes a first entry and additional entries. Each additional entry includes a link reference to a prior entry in the linked list. The link reference for each additional entry all are stored within a content addressable memory. Each additional entry is accessible by performing a content search using the link reference to the prior entry. The linked list is traversed by accessing the first entry in the linked list. A second entry in the linked list is accessed by searching the content addressable memory with an index of the first entry. A third entry in the linked list is accessed by searching the content addressable memory with an index of the second entry.
摘要翻译： 计算系统中的链表结构包括第一条目和附加条目。 每个附加条目包括对链接列表中先前条目的链接引用。 每个附加条目的链接引用全部存储在内容可寻址存储器中。 通过使用前一条目的链接引用执行内容搜索，可以访问每个附加条目。 通过访问链表中的第一个条目遍历链表。 通过用第一条目的索引搜索内容可寻址存储器来访问链表中的第二条目。 通过用第二条目的索引搜索内容可寻址存储器来访问链表中的第三条目。
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公开(公告)号：US5995967A
公开(公告)日：1999-11-30
申请号：US734003
申请日：1996-10-18
CPC分类号： G06F17/30958 , Y10S707/99931
摘要： A linked list structure in a computing system includes a first entry and additional entries. Each additional entry includes a link reference to a prior entry in the linked list. The link reference for each additional entry all are stored within a content addressable memory. Each additional entry is accessible by performing a content search using the link reference to the prior entry. The linked list is traversed by accessing the first entry in the linked list. A second entry in the linked list is accessed by searching the content addressable memory with an index of the first entry. A third entry in the linked list is accessed by searching the content addressable memory with an index of the second entry.
摘要翻译： 计算系统中的链表结构包括第一条目和附加条目。 每个附加条目包括对链接列表中先前条目的链接引用。 每个附加条目的链接引用全部存储在内容可寻址存储器中。 通过使用前一条目的链接引用执行内容搜索，可以访问每个附加条目。 通过访问链表中的第一个条目遍历链表。 通过用第一条目的索引搜索内容可寻址存储器来访问链表中的第二条目。 通过用第二条目的索引搜索内容可寻址存储器来访问链表中的第三条目。
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