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31.发明申请MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIRCUIT DESIGN 失效集成电路设计中的多图形图形识别芯片布局公开(公告)号：US20130086543A1
公开(公告)日：2013-04-04
申请号：US13248711
申请日：2011-09-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/12 , Y02P90/265
摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.
摘要翻译： 在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。 执行细胞运动的全局阶段。 执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位 在为IC设计制作最终布局之前。
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公开(公告)号：US08831875B2
公开(公告)日：2014-09-09
申请号：US13612331
申请日：2012-09-12
申请人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
发明人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
CPC分类号： G08G9/00 , G08G1/0104
摘要： A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure.
摘要翻译： 在说明性实施例中提供了用于解决交通拥堵问题的方法，系统和计算机程序产品。 使用在数据处理系统中使用处理器和存储器执行的应用程序，从一组拥塞的路由部分中选择拥塞的路由部分。 选择一组拥堵车辆，其中，所述一组拥堵车辆通过定位在所选择的拥塞路线部分上而导致所选择的拥塞路线部分中的拥塞。 填充与所选择的拥塞路由部分对应的空位数据结构。 选择一组拥堵车辆的一部分。 拥挤车辆的集合的子集被重新路由到在空缺数据结构中标识的候选路线部分。
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公开(公告)号：US08601425B2
公开(公告)日：2013-12-03
申请号：US13445128
申请日：2012-04-12
申请人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
发明人： Charles Jay Alpert , Zhuo Li , Chin Ngai Sze , Yaoguang Wei
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method, system, and computer program product for solving a congestion problem in an integrated circuit (IC) design are provided in the illustrative embodiments. A congested g-edge is selected from a set of congested g-edges. A set of congesting nets is selected, wherein the set of congesting nets cause congestion in the selected congested g-edges by crossing the selected congested g-edge. A vacancy data structure corresponding to the selected congested g-edge is populated. A subset of the set of the congesting nets is selected. The subset of the set of the congesting nets is rerouted to a candidate g-edge identified in the vacancy data structure.
摘要翻译： 在说明性实施例中提供了用于解决集成电路（IC）设计中的拥塞问题的方法，系统和计算机程序产品。 从一组拥塞的g边缘中选择拥塞的g边。 选择一组拥塞网络，其中所述拥塞网络集合通过穿过所选择的拥塞的g边缘而导致所选择的拥塞的g边缘中的拥塞。 填充与所选择的拥塞的g边缘对应的空位数据结构。 选择一组拥塞网络的子集。 拥塞网络集合的子集被重新路由到在空白数据结构中标识的候选g边。
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34.发明授权Multi-patterning lithography aware cell placement in integrated circuit design 失效集成电路设计中的多图案化光刻感知单元放置公开(公告)号：US08495548B2
公开(公告)日：2013-07-23
申请号：US13248711
申请日：2011-09-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/12 , Y02P90/265
摘要： A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design.
摘要翻译： 在说明性实施例中提供了用于集成电路（IC）设计中的多图案化光刻（MPL）感知单元放置的方法，系统和计算机程序产品。 执行细胞运动的全局阶段。 执行局部相位单元移动，其中本地相位包括从IC设计中的单元行内的单元的多个颜色实例移动单元的颜色实例，其中，每个执行全局相位和局部相位 在为IC设计制作最终布局之前。
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公开(公告)号：US20120240093A1
公开(公告)日：2012-09-20
申请号：US13047492
申请日：2011-03-14
申请人： Charles Jay Alpert , Shiyan Hu , Zhuo Li , Chin Ngai Sze
发明人： Charles Jay Alpert , Shiyan Hu , Zhuo Li , Chin Ngai Sze
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5077
摘要： A method, system, and computer program product for improved routing using layer ranges in the design of an integrated circuit (IC) are provided in the illustrative embodiments. Using an application executing in a data processing system, a score is computed for a net in a set of nets routed using a set of layers in the design. The set of nets is sorted according to scores associated with nets in the set of nets. A layer range from a set of layer ranges is assigned to a net in the sorted list such that a net with a higher than threshold score is assigned a high layer range.
摘要翻译： 在说明性实施例中提供了用于在集成电路（IC）的设计中使用层范围的改进路由的方法，系统和计算机程序产品。 使用在数据处理系统中执行的应用程序，计算使用设计中的一组层路由的一组网络中的网络的得分。 网络集合根据与网络集中的网络相关联的分数进行排序。 来自一组层范围的层范围被分配给排序列表中的网，使得具有高于阈值得分的网被分配高层范围。
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公开(公告)号：US08108819B2
公开(公告)日：2012-01-31
申请号：US12420156
申请日：2009-04-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/08
摘要： A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement.
摘要翻译： 在说明性实施例中提供了用于在集成电路设计中改进的对象放置的方法，系统和计算机可用程序产品。 IC设计包括电池，电池包括电子元件，电线和为IC的互连而定义的引脚。 收到与设计相对应的初始放置。 估计初始放置的特征，其可以包括初始放置区域中的拥塞，针密度或两者。 在初始位置的一部分上进行变换，包括改善特征的区域。 如果转换后的位置的特征有所改善，则会生成与转换的位置对应的最终位置。 该变换可以是调整对象的大小，加权连接，聚集多个对象，缩短由线引导的路线以及在初始放置中矫正线中的弯曲的任何组合。
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公开(公告)号：US20100262944A1
公开(公告)日：2010-10-14
申请号：US12420156
申请日：2009-04-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/08
摘要： A method, system, and computer usable program product for an improved object placement in integrated circuit design are provided in the illustrative embodiments. The IC design includes cells, the cells including electronic components, wires, and pins defined for interconnections of the IC. An initial placement corresponding to the design is received. A characteristic of the initial placement is estimated, which may include congestion, pin density, or both in an area of the initial placement. A transformation is performed on a part of the initial placement including the area to improve the characteristic. If the characteristic has improved in the transformed placement, a final placement corresponding to the transformed placement is produced. The transformation may be any combination of resizing an object, weighting a connection, clustering a plurality of objects, shortening of a route taken by a wire, and straightening a bend in a wire in the initial placement.
摘要翻译： 在说明性实施例中提供了用于在集成电路设计中改进的对象放置的方法，系统和计算机可用程序产品。 IC设计包括电池，电池包括电子元件，电线和为IC的互连而定义的引脚。 收到与设计相对应的初始放置。 估计初始放置的特征，其可以包括初始放置区域中的拥塞，针密度或两者。 在初始位置的一部分上进行变换，包括改善特征的区域。 如果转换后的位置的特征有所改善，则会生成与转换的位置对应的最终位置。 该变换可以是调整对象的大小，加权连接，聚集多个对象，缩短由线引导的路线以及在初始放置中矫正线中的弯曲的任何组合。
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公开(公告)号：US07464356B2
公开(公告)日：2008-12-09
申请号：US11304955
申请日：2005-12-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to control the movement of different cells to reduce the density of the cells prior to legalization of the cell placement.
摘要翻译： 一种集成电路设计中的细胞放置方法，其使用从密度值确定的计算的扩散速度，以便重新定位细胞，直到细胞放置将密度降低到低于预定阈值。 该方法用于控制不同细胞的运动，以在细胞放置合法化之前降低细胞的密度。
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公开(公告)号：US07020861B2
公开(公告)日：2006-03-28
申请号：US10621950
申请日：2003-07-17
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5072
摘要： A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and non-latched objects. The algorithm places objects to minimize clock signal delay subject to a constraint on the placement distribution of the latched objects relative to the placement distribution of the non-latched objects. The latched object and non-latched object placement constraints may limit the difference between the latched object center of mass and a non-latched object center of mass. The latched object center of mass equals a sum of size-location products for each latched object divided by the sum of sizes for each latched object. The constraints may require that the latched object center of mass and the non-latched center of mass both equal the center of mass for all objects.
摘要翻译： 一种设计集成电路的方法，包括执行放置算法以将一组对象放置在集成电路内。 对象集包括锁存对象和非锁定对象。 该算法使对象最小化时钟信号延迟，受限于锁存对象相对于非锁定对象的位置分布的位置分布。 锁定对象和非锁定对象放置约束可能会限制被锁定的物体质心和未锁定的物体质心之间的差异。 被锁定的物体质心等于每个被锁定物体的大小位置乘积之和除以每个锁定物体的大小之和。 约束可能要求被锁定的物体质心和非锁定质心均等于所有物体的质心。
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40.发明授权Optimal buffered routing path constructions for single and multiple clock domains systems 有权用于单时钟和多时钟域系统的最优缓冲路由路径结构公开(公告)号：US06915361B2
公开(公告)日：2005-07-05
申请号：US10264165
申请日：2002-10-03
申请人： Charles Jay Alpert , Soha Hassoun
发明人： Charles Jay Alpert , Soha Hassoun
CPC分类号： G06F17/5077
摘要： A method, computer program product, and data processing system for automatically designing routing paths in an integrated circuit is disclosed. The present invention allows for the design of paths that are optimal in terms of the signal delay in circuits that may require registers for signal to travel over multiple clock cycles or in circuits that may contain multiple clock domains.An integrated circuit die is modeled as a weighted grid graph in which the edges represent wire segments and the weights represent the delays associated with those wire segments. Designing for optimum delay involves finding a shortest path between two vertices in the grid graph using a modified single-source shortest path algorithm. Registers, buffers, and dual-clock domain synchronizers are modeled according to a labeling function that assigns components to selected vertices in the routing path for optimal results.
摘要翻译： 公开了一种用于在集成电路中自动设计路由路径的方法，计算机程序产品和数据处理系统。 本发明允许设计在电路中的信号延迟方面是最佳的，可能需要用于信号在多个时钟周期上行进的寄存器或者可能包含多个时钟域的电路中的信号延迟。 集成电路管芯被建模为加权网格图，其中边缘表示线段，权重表示与那些线段相关联的延迟。 设计最佳延迟涉及使用修改的单源最短路径算法在网格图中的两个顶点之间找到最短路径。 寄存器，缓冲区和双时钟域同步器根据标记功能进行建模，该标签功能将组件分配到路由路径中的所选顶点以获得最佳结果。
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