Abstract:
A system for adjusting late collision slot time is provided in a network interface having a media access control (MAC) engine that performs collision detection. The MAC engine comprises a MAC transmit block that transmits frames via a media independent interface (MII) to an ektemal physical layer device (PHY) coupled to the MII, and a MAC receive block for receiving frames from the PHY. A MAC control register is configured for storing ablate collision time slot adjustment value used to adjust the late collision slot time. The late collision time slot adjustment value is programmed to compensate for variations in internal delays of PHYs that may be connected to the MII.
Abstract:
An m bit counter which counts to a desired clock frequency F.sub.D given a central clock frequency F.sub.C is emulated by a chain of two subcounters. The ratio r of the central clock frequency F.sub.C over the desired clock frequency F.sub.D is factored to r=F.sub.C /F.sub.D =2.sup.n * p, where n is one of zero or an integer (i.e., 0, 1, 2, 3 . . . ) and where p is an integer. A 1 to p subcounter counts from 1 to p driven by the central clock frequency F.sub.C. The output of the 1 to p counter is an intermediate clock frequency which includes a pulse every periodic count from 1 to p. The intermediate clock frequency drives a m+n bit subcounter with the n bits being appended as the least significant bits of the m+n bit subcounter. In this manner, the m most significant bits of the m+n bit subcounter count to the desired clock frequency F.sub.D.
Abstract:
A network interface for a workstation, configured to be powered down to a standby mode while the network interface remains in a powered-up condition, includes a bypass circuit configured to enable configuration registers in the network interface to complete loading of configuration information in a known state, regardless of an absence of an external data clock from the network during the initialization interval. The bypass circuit ensures that the configuration registers in the network interface that require a network clock (e.g., a transmit clock or a receive clock) are maintained in a known state to enable the network interface to be independently initialized. One example of the bypass circuit holds a power on reset signal until the necessary network clock signal is detected for a predetermined number of detected clock cycles. Another example of the bypass circuit substitutes the absent clock signal with an independent clock source in response to the power on reset signal and holds the power on reset signal for a predetermined number of independent clock cycles, followed by switching back to the signal path providing the required clock signal. The disclosed arrangement enables the network interface device to initialize upon power up and start to monitor network media for wakeup traffic indicating the host computer in the workstation should be activated.
Abstract:
An apparatus and method for remote wake-up of an intended node within a data exchange system having interlinked networks (e.g., router-interlinked LAN's) is disclosed. A wake-up commanding format is disclosed wherein a sequence corresponding to the address of the intended node is embedded N consecutive times (e.g., at least 16 consecutive times) extensively through the respective data fields of one or more packets sent from a remote source node to the intended node. When this particular sequence is received by the intended node while the intended node is in a sleep mode, a wake-up operation is responsively initiated so that the sleeping node will awaken, at least for a time, to respond to future received packets.
Abstract:
Roughly described, a network interface device is assigned a maximum extent-of-search. A hash function is applied to the header information of each incoming packet, to generate a hash code for the packet. The hash code designates a particular subset of the table within which the particular header information should be found, and an iterative search is made within that subset. If the search locates a matching entry before the search limit is exceeded, then the incoming data packet is delivered to the receive queue identified in the matching entry. But if the search reaches the search limit before a matching entry is located, then device delivers the packet to a default queue, such as a kernel queue, in the host computer system. The kernel is then responsible for delivering the packet to the correct endpoint.
Abstract:
Roughly described, a network interface device receiving data packets from a computing device for transmission onto a network, the data packets having a certain characteristic, transmits the packet only if the sending queue has authority to send packets having that characteristic. The data packet characteristics can include transport protocol number, source and destination port numbers, source and destination IP addresses, for example. Authorizations can be programmed into the NIC by a kernel routine upon establishment of the transmit queue, based on the privilege level of the process for which the queue is being established. In this way, a user process can use an untrusted user-level protocol stack to initiate data transmission onto the network, while the NIC protects the remainder of the system or network from certain kinds of compromise.
Abstract:
In a pressurized water reactor with all of the in-core instrumentation gaining access to the core through the reactor head, each fuel assembly in which the instrumentation is introduced is aligned with an upper internals instrumentation guide-way. In the elevations above the upper internals upper support assembly, the instrumentation is protected and aligned by upper mounted instrumentation columns that are part of the instrumentation guide-way and extend from the upper support assembly towards the reactor head in hue with a corresponding head penetration. The upper mounted instrumentation columns are supported laterally at one end by an upper guide tube and at the other end by the upper support plate.
Abstract:
Roughly described, method for managing data transmission between a host subsystem and a network interface device, in which the host writes data buffer descriptors into a DMA descriptor queue, and the network interface device writes completion events to notify the host when it has completed processing of data buffers. Each of the completion event descriptors notify the host of completion of data transfer between the NIC and one or more of the data buffers, and can also embed a queue empty notification inside the completion event.
Abstract:
An over-current protection device includes a current-sensitive element, two insulating layers and two electrode layers. The current-sensitive element comprises two electrode foils and a current-sensitive layer laminated between the two electrode foils, where the current-sensitive layer has the behavior of positive temperature coefficient. The two insulating layers are stacked on the upper and lower surfaces of the current-sensitive element, respectively, and the glass switching temperature thereof is between 90-120° C. or the heat dissipation rate is between 1-7W/° C.-m. The two electrode layers are connected to the two ends of the current-sensitive element, respectively.
Abstract:
An over-current protection device comprises at least one PTC component, at least one thermal dissipation layer, at least one adhesive layer and at least two isolation layers, wherein the PTC component is formed by interposing a PTC material between two electrode layers. The at least one adhesive layer as a thermal conductive medium is interposed between the PTC component and at least one thermal dissipation layer to combine them. The at least two isolation layers separate the thermal dissipation layer, adhesive layer and electrode layers into two electrical independent portions.