System and method for programming late collision slot time
    31.
    发明授权
    System and method for programming late collision slot time 失效
    用于编程后期碰撞槽时间的系统和方法

    公开(公告)号:US06229817B1

    公开(公告)日:2001-05-08

    申请号:US08993127

    申请日:1997-12-18

    CPC classification number: H04L12/40032 H04L12/413

    Abstract: A system for adjusting late collision slot time is provided in a network interface having a media access control (MAC) engine that performs collision detection. The MAC engine comprises a MAC transmit block that transmits frames via a media independent interface (MII) to an ektemal physical layer device (PHY) coupled to the MII, and a MAC receive block for receiving frames from the PHY. A MAC control register is configured for storing ablate collision time slot adjustment value used to adjust the late collision slot time. The late collision time slot adjustment value is programmed to compensate for variations in internal delays of PHYs that may be connected to the MII.

    Abstract translation: 在具有执行冲突检测的媒体访问控制(MAC)引擎的网络接口中提供了一种用于调整后期冲突时隙时间的系统。 MAC引擎包括通过媒体独立接口(MII)向耦合到MII的物理层设备(PHY)发送帧的MAC传输块,以及用于从PHY接收帧的MAC接收块。 配置MAC控制寄存器,用于存储用于调整后期冲突时隙时间的切换冲突时隙调整值。 后期冲突时隙调整值被编程以补偿可能连接到MII的PHY的内部延迟的变化。

    Emulation of an m bit counter driven by a desired clock frequency given
a central clock frequency
    32.
    发明授权
    Emulation of an m bit counter driven by a desired clock frequency given a central clock frequency 失效
    由给定中心时钟频率的期望时钟频率驱动的m位计数器的仿真

    公开(公告)号:US5966421A

    公开(公告)日:1999-10-12

    申请号:US989435

    申请日:1997-12-12

    CPC classification number: H03K23/66 H03K21/00

    Abstract: An m bit counter which counts to a desired clock frequency F.sub.D given a central clock frequency F.sub.C is emulated by a chain of two subcounters. The ratio r of the central clock frequency F.sub.C over the desired clock frequency F.sub.D is factored to r=F.sub.C /F.sub.D =2.sup.n * p, where n is one of zero or an integer (i.e., 0, 1, 2, 3 . . . ) and where p is an integer. A 1 to p subcounter counts from 1 to p driven by the central clock frequency F.sub.C. The output of the 1 to p counter is an intermediate clock frequency which includes a pulse every periodic count from 1 to p. The intermediate clock frequency drives a m+n bit subcounter with the n bits being appended as the least significant bits of the m+n bit subcounter. In this manner, the m most significant bits of the m+n bit subcounter count to the desired clock frequency F.sub.D.

    Abstract translation: 计数到给定中心时钟频率FC的期望时钟频率FD的m位计数器由两个子计数器的链模拟。 中心时钟频率FC在期望时钟频率FD上的比率r被推定为r = FC / FD = 2n * p,其中n是零或整数之一(即,0,1,2,3,..., ),其中p是整数。 1到p个子计数器从1到p由中央时钟频率FC驱动。 1到p计数器的输出是一个中间时钟频率,每个周期性计数从1到p包括一个脉冲。 中间时钟频率驱动m + n位子计数器,附加n位作为m + n位子计数器的最低有效位。 以这种方式,m + n位子计数器的m个最高有效位计数到期望的时钟频率FD。

    Apparatus and method for selectively controlling clocking and resetting
of a network interface
    33.
    发明授权
    Apparatus and method for selectively controlling clocking and resetting of a network interface 失效
    用于选择性地控制网络接口的时钟和复位的装置和方法

    公开(公告)号:US5938728A

    公开(公告)日:1999-08-17

    申请号:US961190

    申请日:1997-10-30

    CPC classification number: G06F1/24

    Abstract: A network interface for a workstation, configured to be powered down to a standby mode while the network interface remains in a powered-up condition, includes a bypass circuit configured to enable configuration registers in the network interface to complete loading of configuration information in a known state, regardless of an absence of an external data clock from the network during the initialization interval. The bypass circuit ensures that the configuration registers in the network interface that require a network clock (e.g., a transmit clock or a receive clock) are maintained in a known state to enable the network interface to be independently initialized. One example of the bypass circuit holds a power on reset signal until the necessary network clock signal is detected for a predetermined number of detected clock cycles. Another example of the bypass circuit substitutes the absent clock signal with an independent clock source in response to the power on reset signal and holds the power on reset signal for a predetermined number of independent clock cycles, followed by switching back to the signal path providing the required clock signal. The disclosed arrangement enables the network interface device to initialize upon power up and start to monitor network media for wakeup traffic indicating the host computer in the workstation should be activated.

    Abstract translation: 一种用于工作站的网络接口,被配置为在网络接口保持处于上电状态时被关闭到待机模式,该旁路电路被配置为使网络接口中的配置寄存器能够完成对已知的配置信息的加载 状态,而不管在初始化间隔期间是否存在来自网络的外部数据时钟。 旁路电路确保需要网络时钟(例如,发送时钟或接收时钟)的网络接口中的配置寄存器被保持在已知状态,以使得能够独立地初始化网络接口。 旁路电路的一个示例保持上电复位信号,直到在预定数量的检测到的时钟周期内检测到必要的网络时钟信号。 旁路电路的另一个例子是响应于上电复位信号而将不存在的时钟信号替换为独立的时钟源,并将上电复位信号保持预定数量的独立时钟周期,随后切换回提供 所需的时钟信号。 所公开的布置使得网络接口设备能够在上电时进行初始化,并开始监视网络媒体的唤醒流量,指示工作站中的主计算机应被激活。

    Apparatus and method for remote wake-up in system having interlinked
networks
    34.
    发明授权
    Apparatus and method for remote wake-up in system having interlinked networks 失效
    具有互连网络的系统中用于远程唤醒的装置和方法

    公开(公告)号:US5835719A

    公开(公告)日:1998-11-10

    申请号:US972093

    申请日:1997-11-17

    CPC classification number: G06F1/3209 H04L12/12 Y02B60/32 Y02B60/34

    Abstract: An apparatus and method for remote wake-up of an intended node within a data exchange system having interlinked networks (e.g., router-interlinked LAN's) is disclosed. A wake-up commanding format is disclosed wherein a sequence corresponding to the address of the intended node is embedded N consecutive times (e.g., at least 16 consecutive times) extensively through the respective data fields of one or more packets sent from a remote source node to the intended node. When this particular sequence is received by the intended node while the intended node is in a sleep mode, a wake-up operation is responsively initiated so that the sleeping node will awaken, at least for a time, to respond to future received packets.

    Abstract translation: 公开了一种用于在具有互连网络(例如,路由器互连LAN)的数据交换系统内远程唤醒预期节点的装置和方法。 公开了一种唤醒命令格式,其中对应于预期节点的地址的序列通过从远程源节点发送的一个或多个分组的相应数据字段被广泛地连续N次(例如,至少16个连续时间) 到目标节点。 当预期节点处于睡眠模式时,当预定节点接收到该特定序列时,响应地启动唤醒操作,使得休眠节点至少在一段时间内唤醒以响应未来接收到的分组。

    PACKET VALIDATION IN VIRTUAL NETWORK INTERFACE ARCHITECTURE
    36.
    发明申请
    PACKET VALIDATION IN VIRTUAL NETWORK INTERFACE ARCHITECTURE 有权
    虚拟网络接口架构中的分组验证

    公开(公告)号:US20140059221A1

    公开(公告)日:2014-02-27

    申请号:US13765579

    申请日:2013-02-12

    Abstract: Roughly described, a network interface device receiving data packets from a computing device for transmission onto a network, the data packets having a certain characteristic, transmits the packet only if the sending queue has authority to send packets having that characteristic. The data packet characteristics can include transport protocol number, source and destination port numbers, source and destination IP addresses, for example. Authorizations can be programmed into the NIC by a kernel routine upon establishment of the transmit queue, based on the privilege level of the process for which the queue is being established. In this way, a user process can use an untrusted user-level protocol stack to initiate data transmission onto the network, while the NIC protects the remainder of the system or network from certain kinds of compromise.

    Abstract translation: 大体上描述了一种从计算设备接收数据包以便传输到网络上的网络接口设备,具有一定特性的数据分组仅在发送队列具有发送具有该特性的分组的权限时发送分组。 数据包特征可以包括传输协议号,源和目的端口号,源和目的IP地址。 基于建立队列的进程的权限级别,可以通过内核例程在建立传输队列时将授权编程到NIC中。 以这种方式,用户进程可以使用不受信任的用户级协议栈来发起到网络上的数据传输,而NIC保护系统或网络的其余部分免受某些种类的折中。

    Upper internals arrangement for a pressurized water reactor
    37.
    发明授权
    Upper internals arrangement for a pressurized water reactor 有权
    压力水反应堆的上部内部装置

    公开(公告)号:US08483347B2

    公开(公告)日:2013-07-09

    申请号:US11733248

    申请日:2007-04-10

    Abstract: In a pressurized water reactor with all of the in-core instrumentation gaining access to the core through the reactor head, each fuel assembly in which the instrumentation is introduced is aligned with an upper internals instrumentation guide-way. In the elevations above the upper internals upper support assembly, the instrumentation is protected and aligned by upper mounted instrumentation columns that are part of the instrumentation guide-way and extend from the upper support assembly towards the reactor head in hue with a corresponding head penetration. The upper mounted instrumentation columns are supported laterally at one end by an upper guide tube and at the other end by the upper support plate.

    Abstract translation: 在具有所有核心仪器的压水反应器中,通过反应器头部进入核心,将引入仪器的每个燃料组件与上部内部仪器仪表导轨对准。 在上部内部上部支撑组件上方的高度中,仪器由作为仪表导向器一部分的上部安装的仪表柱保护和对准,并且从上部支撑组件朝向反应器头部以色调以相应的头部穿透延伸。 上部安装的仪器支架在一端通过上导向管横向支撑,另一端由上支撑板支撑。

    Including descriptor queue empty events in completion events
    38.
    发明授权
    Including descriptor queue empty events in completion events 有权
    在完成事件中包括描述符队列空事件

    公开(公告)号:US07831749B2

    公开(公告)日:2010-11-09

    申请号:US11050474

    申请日:2005-02-03

    CPC classification number: G06F9/4812 G06F13/28 G06F13/32 G06F13/385

    Abstract: Roughly described, method for managing data transmission between a host subsystem and a network interface device, in which the host writes data buffer descriptors into a DMA descriptor queue, and the network interface device writes completion events to notify the host when it has completed processing of data buffers. Each of the completion event descriptors notify the host of completion of data transfer between the NIC and one or more of the data buffers, and can also embed a queue empty notification inside the completion event.

    Abstract translation: 大体描述了用于管理主机子系统和网络接口设备之间的数据传输的方法,其中主机将数据缓冲器描述符写入DMA描述符队列,并且网络接口设备写入完成事件以在主机完成处理 数据缓冲区。 每个完成事件描述符通知主机NIC和一个或多个数据缓冲区之间的数据传输完成,并且还可以在完成事件中嵌入队列空通知。

    Over-current protection device
    39.
    发明申请
    Over-current protection device 审中-公开
    过电流保护装置

    公开(公告)号:US20050128046A1

    公开(公告)日:2005-06-16

    申请号:US11000788

    申请日:2004-12-01

    Applicant: Zack Lin Ching Yu

    Inventor: Zack Lin Ching Yu

    CPC classification number: H01C1/148 H01C7/027

    Abstract: An over-current protection device includes a current-sensitive element, two insulating layers and two electrode layers. The current-sensitive element comprises two electrode foils and a current-sensitive layer laminated between the two electrode foils, where the current-sensitive layer has the behavior of positive temperature coefficient. The two insulating layers are stacked on the upper and lower surfaces of the current-sensitive element, respectively, and the glass switching temperature thereof is between 90-120° C. or the heat dissipation rate is between 1-7W/° C.-m. The two electrode layers are connected to the two ends of the current-sensitive element, respectively.

    Abstract translation: 过流保护装置包括电流敏感元件,两个绝缘层和两个电极层。 电流敏感元件包括两个电极箔和层压在两个电极箔之间的电流敏感层,其中电流敏感层具有正温度系数的行为。 两个绝缘层分别堆叠在电流敏感元件的上表面和下表面上,玻璃切换温度在90-120℃之间或散热率在1-7W /℃之间。 m。 两个电极层分别连接到电流敏感元件的两端。

    Over-current protection device and manufacturing method thereof
    40.
    发明申请
    Over-current protection device and manufacturing method thereof 有权
    过流保护装置及其制造方法

    公开(公告)号:US20050094347A1

    公开(公告)日:2005-05-05

    申请号:US10978856

    申请日:2004-11-01

    Applicant: Zack Lin Ching Yu

    Inventor: Zack Lin Ching Yu

    CPC classification number: H01C1/08 H01C1/1406 H01C7/02

    Abstract: An over-current protection device comprises at least one PTC component, at least one thermal dissipation layer, at least one adhesive layer and at least two isolation layers, wherein the PTC component is formed by interposing a PTC material between two electrode layers. The at least one adhesive layer as a thermal conductive medium is interposed between the PTC component and at least one thermal dissipation layer to combine them. The at least two isolation layers separate the thermal dissipation layer, adhesive layer and electrode layers into two electrical independent portions.

    Abstract translation: 过电流保护装置包括至少一个PTC部件,至少一个散热层,至少一个粘合剂层和至少两个隔离层,其中PTC部件通过在两个电极层之间插入PTC材料形成。 作为导热介质的至少一个粘合剂层插入在PTC部件和至少一个散热层之间以将它们组合。 至少两个隔离层将散热层,粘合剂层和电极层分成两个电独立部分。

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