公开(公告)号：US20090122558A1

公开(公告)日：2009-05-14

申请号：US12010461

申请日：2008-01-25

Applicant: Ching-Cheng Tsai ,  Chia-Hsin Chen

Inventor： Ching-Cheng Tsai ,  Chia-Hsin Chen

IPC: F21V7/00

CPC classification number: H04M1/23 ,  F21Y2115/10 ,  G02B6/0055 ,  H01H2219/014 ,  H01H2219/044 ,  H01H2221/07 ,  H04M1/22

Abstract: An energy-saving light-emitting module is provided, comprising: a light guide plate having a light-incident surface, a bottom surface intersecting the light-incident surface and a light-emitting surface opposite the bottom surface, wherein a plurality of recesses are provided at the bottom surface; a light source placed at one side of the light-incident surface of the light guide plate; and a reflective plate placed at the bottom of the light guide plate for reflecting light rays from the light source into the light guide plate. The light rays emitted by the light source reach the arc surface of each recess at the bottom side of the light guide plate, and the light rays are then reflected to the light-emitting surface. Meanwhile, during the light-emitting process, light rays are concentrated at the arc surface of each recess. The concentration of light rays increases overall luminance produced by the module, and thus, energy is saved effectively.

Abstract translation: 提供了一种节能发光模块，包括：具有光入射面的导光板，与光入射面交叉的底面和与所述底面相反的发光面，其中，多个凹部为 设在底面; 放置在所述导光板的光入射面的一侧的光源; 以及放置在导光板的底部的反射板，用于将来自光源的光线反射到导光板中。 由光源发出的光线到达导光板底面的各凹部的圆弧面，然后将光线反射到发光面。 同时，在发光过程中，光线集中在每个凹部的弧形表面。 光线的浓度增加了由模块产生的整体亮度，从而有效地节省了能量。

公开(公告)号：US20080315690A1

公开(公告)日：2008-12-25

申请号：US12040931

申请日：2008-03-03

Applicant: Leaf Chen ,  Chih-Shun Lee ,  Chia-Hsin Chen

Inventor： Leaf Chen ,  Chih-Shun Lee ,  Chia-Hsin Chen

IPC: H01H47/00

CPC classification number: H03K17/6872 ,  H03K19/0016 ,  H03K2217/0036 ,  Y10T307/76

Abstract: An initial circuit is provided. The initial circuit receives a plurality of input signals and controls an initial status of a switching circuit with a plurality of switches. The initial circuit includes a judgment circuit for generating an enable signal according to one of the input signals, and a control circuit for generating a plurality of control signals according to the enable signal and the input signals. The switches are turned off by the control circuit according to the control signals when the switching circuit is in an initial status, and the switches are controlled by the control circuit according to the control signals when the switching circuit is in an operating status.

Abstract translation: 提供初始电路。 初始电路接收多个输入信号，并利用多个开关控制开关电路的初始状态。 初始电路包括用于根据输入信号之一产生使能信号的判断电路，以及根据使能信号和输入信号产生多个控制信号的控制电路。 当开关电路处于初始状态时，开关由控制电路根据控制信号关断，开关由切换电路处于运行状态时根据控制信号由控制电路控制。

公开(公告)号：US07358882B2

公开(公告)日：2008-04-15

申请号：US11424612

申请日：2006-06-16

Applicant: Chia-Hsin Chen ,  Chiu-Yuan Lin ,  Bor-Yuh Chang

Inventor： Chia-Hsin Chen ,  Chiu-Yuan Lin ,  Bor-Yuh Chang

IPC: H03M1/66

CPC classification number: H04N5/14

Abstract: A video processing method and apparatus to employing an analog user interface and a digital video decoder. A working mode is provided, according to which analog control signals from the analog user interface are selectively directed to an analog-to-digital converter. The analog control signal is converted to digital control signal to accordingly control the digital video decoder.

Abstract translation: 一种采用模拟用户界面和数字视频解码器的视频处理方法和装置。 提供工作模式，根据该工作模式，来自模拟用户界面的模拟控制信号被选择性地引导到模数转换器。 模拟控制信号被转换为数字控制信号，从而相应地控制数字视频解码器。

公开(公告)号：US20070206882A1

公开(公告)日：2007-09-06

申请号：US11424547

申请日：2006-06-16

Applicant: Chia-Hsin Chen

Inventor： Chia-Hsin Chen

IPC: G06K9/32

CPC classification number: G06T3/4007

Abstract: A method for reducing the size of an image suitable for an image data having a plurality of pixels is provided. The method of the present invention comprises the following steps. First, an image data is divided into a plurality of sampling areas, and each sampling area has a predetermined number of pixels. When the image data is an odd field, a right weighting for each pixel in every sampling area is configured according to a first predetermined ratio, such that each sampling area is able to generate a first sampling pixel. When the image data is an even field, a right weighting for each pixel in every sampling area is configured according to a second predetermined ratio, such that each sampling area is able to generate a second sampling pixel. Then, a new image data is generated according to the first and second sampling pixels.

Abstract translation: 提供了一种用于减小适合于具有多个像素的图像数据的图像尺寸的方法。 本发明的方法包括以下步骤。 首先，将图像数据分割为多个采样区域，每个采样区域具有预定数量的像素。 当图像数据是奇数场时，根据第一预定比例配置每个采样区域中的每个像素的右加权，使得每个采样区域能够生成第一采样像素。 当图像数据是偶数场时，根据第二预定比例配置每个采样区域中的每个像素的右加权，使得每个采样区域能够生成第二采样像素。 然后，根据第一和第二采样像素生成新的图像数据。

公开(公告)号：US20070192517A1

公开(公告)日：2007-08-16

申请号：US11308890

申请日：2006-05-23

Applicant: Bor-Yuh Chang ,  Chiu-Yuan Lin ,  Chia-Hsin Chen

Inventor： Bor-Yuh Chang ,  Chiu-Yuan Lin ,  Chia-Hsin Chen

IPC: G06F13/38

CPC classification number: H04N21/4586 ,  G06F8/65 ,  H04N21/41422 ,  H04N21/818

Abstract: An Audiovisual equipment comprises a data input interface, an analog-to-digital (AD) converter, a retrieving circuit and a processing unit burnt with program codes is provided. The data input interface receives analog data from a data source carrying updating data therein. The A/D converter converts the analog data into digital data which is then transmitted to the retrieving circuit. The retrieving circuit retrieves updating data and then transfers it to the processing unit. The processing unit updates the program codes using the updating data.

Abstract translation: 视听设备包括数据输入接口，模数（AD）转换器，检索电路和用程序代码烧毁的处理单元。 数据输入接口从其中承载更新数据的数据源接收模拟数据。 A / D转换器将模拟数据转换成数字数据，然后发送到检索电路。 检索电路检索更新数据，然后将其传送到处理单元。 处理单元使用更新数据更新程序代码。

公开(公告)号：US20060274739A1

公开(公告)日：2006-12-07

申请号：US11142283

申请日：2005-06-02

Applicant: Chia-Hsin Chen

Inventor： Chia-Hsin Chen

IPC: H04L12/56 ,  H04L12/43

CPC classification number: H04L29/12009 ,  H04L29/12839 ,  H04L45/7453 ,  H04L49/90 ,  H04L49/901 ,  H04L61/6022

Abstract: A method for managing medium access control (MAC) address and related apparatus are provided, including an MAC address learning method and an MAC addresses inquiring method. The learning method includes the steps of: mapping an MAC address to a designated slot and a companion slot in an address table; if said designated slot being empty, learning said MAC address into said designated slot; and if said designated slot being non-empty, said companion slot being empty and the content of said designated slot being non-static, moving the content of said designated slot to said companion slot and modifying a bit of the higher part of said MAC address in said companion slot and learning said MAC address into said designated slot. The inquiring method includes the steps of: mapping an MAC address to a designated slot and a companion slot of an address table; reading a first content of said designated slot and a second content of said companion slot; selectively restoring said second content; comparing said MAC address with said first content and said MAC address with said restored second content; and generating an inquiry result according to said comparisons.

Abstract translation: 提供了一种用于管理介质访问控制（MAC）地址和相关装置的方法，包括MAC地址学习方法和MAC地址查询方法。 该学习方法包括以下步骤：将MAC地址映射到地址表中的指定时隙和伴随时隙; 如果所述指定的时隙是空的，则将所述MAC地址学习到所述指定的时隙中; 并且如果所述指定时隙不为空，则所述伴随时隙为空，并且所述指定时隙的内容是非静态的，将所述指定时隙的内容移动到所述伴随时隙，并修改所述MAC地址的较高部分的一位 在所述伴侣时隙中，将所述MAC地址学习到所述指定时隙。 查询方法包括以下步骤：将MAC地址映射到地址表的指定时隙和伴随时隙; 读取所述指定时隙的第一内容和所述伴随时隙的第二内容; 选择性地恢复所述第二内容; 将所述MAC地址与所述第一内容和所述MAC地址与所述恢复的第二内容进行比较; 并根据所述比较生成查询结果。

公开(公告)号：US07034840B2

公开(公告)日：2006-04-25

申请号：US10692683

申请日：2003-10-27

Applicant: Chia-Hsin Chen

Inventor： Chia-Hsin Chen

IPC: G09G5/36 ,  G06T1/60 ,  G06F13/00

CPC classification number: G09G5/391 ,  G09G2340/145

Abstract: A method for an image reducing processing circuit includes the memory architecture of two FIFO units. The method includes the following steps of: providing an input processing unit receiving original image data and delivering the image data; providing a horizontal direction image processing unit receiving the image data from the input processing unit; providing a first step FIFO unit receiving the image data from the horizontal direction image processing unit to read and write the image data on the same access frequency; providing a vertical direction image processing unit receiving the image data from the first step FIFO unit; providing a second step FIFO unit receiving the image data from the vertical direction image processing unit and implementing the readout/writing of the image data on two access frequency, and providing an output processing unit receiving the image data from the second step FIFO unit and outputting reduced image.

Abstract translation: 一种图像缩小处理电路的方法包括两个FIFO单元的存储架构。 该方法包括以下步骤：提供接收原始图像数据并传送图像数据的输入处理单元; 提供从所述输入处理单元接收所述图像数据的水平方向图像处理单元; 提供从水平方向图像处理单元接收图像数据以在相同的存取频率上读取和写入图像数据的第一级FIFO单元; 提供从所述第一步骤FIFO单元接收所述图像数据的垂直方向图像处理单元; 提供从垂直方向图像处理单元接收图像数据并实现在两个存取频率上的图像数据的读出/写入的第二步骤FIFO单元，并且提供从第二步FIFO单元接收图像数据的输出处理单元并输出 缩小图像。

公开(公告)号：US20050094658A1

公开(公告)日：2005-05-05

申请号：US10960085

申请日：2004-10-08

Applicant: Jen-Kai Chen ,  Chia-Hsin Chen

Inventor： Jen-Kai Chen ,  Chia-Hsin Chen

IPC: H04L12/56

CPC classification number: H04L49/201 ,  H04L49/351

Abstract: A method for transmitting multi-cast packets is provided, including the steps of (a) receiving a plurality of multi-cast packets and generating corresponding port masks to indicate a plurality of ports from which the multi-cast packets are to be transmitted, (b) selecting, based on the yet-enqueued ports indicated in port masks, a port with highest priority, enqueuing the multi-cast packet into the port, and updating the port masks, (c) checking whether the port with highest priority being full-duplex, and (d) determining when to repeat steps (b) to (d) base on the result of the checking, until finishing the transmission specified by the port masks. In step (d), when the port with highest priority is full-duplex, wait until the port with highest priority starting transmitting the packet, then repeat steps (b) to (d). On the other hand, when the port with highest priority is half-duplex, wait until the port with highest priority transmitting a certain portion of the packet, for example 64 bytes or 128 bytes, then repeat steps (b) to (d). This will repeat until finishing all the transmission specified by the port masks. Preferably, the port with highest priority means the port of the highest priority group with the shortest output queue. When finishing all the transmission specified by the port masks, the switch will release all the related buffers of the multi-cast packets.

Abstract translation: 提供了一种用于发送多播分组的方法，包括以下步骤：（a）接收多个多播分组并生成相应的端口掩码，以指示要从中发送多播分组的多个端口（ b）根据端口掩码中指定的入口端口选择具有最高优先级的端口，将多播数据包排入端口，并更新端口掩码，（c）检查优先级最高的端口是否满 -duplex，以及（d）根据检查结果确定何时重复步骤（b）至（d），直到完成由端口掩码指定的传输。 在步骤（d）中，当优先级最高的端口为全双工时，请等待具有最高优先级的端口开始发送数据包，然后重复步骤（b）至（d）。 另一方面，当具有最高优先级的端口是半双工时，等待直到具有最高优先级的端口发送分组的某一部分，例如64字节或128字节，然后重复步骤（b）至（d）。 这将重复，直到完成由端口掩码指定的所有传输。 优选地，优先级最高的端口表示具有最短输出队列的最高优先级组的端口。 当完成端口掩码指定的所有传输时，交换机将释放多播数据包的所有相关缓冲区。

公开(公告)号：US06738880B2

公开(公告)日：2004-05-18

申请号：US09878896

申请日：2001-06-11

Applicant: Jiin Lai ,  Chia-Hsin Chen ,  Nai-Shung Chang

Inventor： Jiin Lai ,  Chia-Hsin Chen ,  Nai-Shung Chang

IPC: G06F1300

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087

Abstract: A buffer for varying data access speed. Combining the buffer with a memory such as a double data rate synchronous dynamic random access memory, the data transmission rate of a memory system can be enhanced. The buffer is coupled with a control chip set and several memory modules to provide functions of data analysis and assembly to satisfy a two-way data transmission interface and to obtain a higher data transmission rate. The buffer also has the function of isolating the electric connection between two sides. A single signal interface from a memory module can be converted to a complementary source synchronous signal by the buffer, so that a high-speed data transmission can be achieved. A memory system can apply several of such buffers to achieve an even higher data transmission speed.

Abstract translation: 一种用于改变数据访问速度的缓冲区。 将缓冲器与诸如双倍数据速率同步动态随机存取存储器的存储器组合，可以提高存储器系统的数据传输速率。 缓冲器与控制芯片组和多个存储器模块耦合，以提供数据分析和组装的功能，以满足双向数据传输接口并获得更高的数据传输速率。 缓冲器还具有隔离两侧电气连接的功能。 来自存储器模块的单个信号接口可以由缓冲器转换成互补源同步信号，从而可以实现高速数据传输。 存储器系统可以应用若干这样的缓冲器以实现甚至更高的数据传输速度。

公开(公告)号：US06490665B1

公开(公告)日：2002-12-03

申请号：US09350974

申请日：1999-07-09

Applicant: Jiin Lai ,  Chih-kuo Kao ,  Chia-Hsin Chen

Inventor： Jiin Lai ,  Chih-kuo Kao ,  Chia-Hsin Chen

IPC: G06F1200

CPC classification number: G06F12/0895 ,  G06F12/123

Abstract: A memory-access management method and system is provided for use with an SDRAM (Synchronous Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system includes a page-table register unit including a page table for storing a predefined number of recently accessed memory locations of the memory unit. Further, the memory-page management system includes a comparison unit capable of, in response to each access request to the memory unit, checking whether the requested memory location is a hit to any one stored in the page table in the page-table register unit. A utilization-rate register unit is coupled to the page-table register unit for monitoring the least-recently-used records stored in the page-table register unit; and moreover, a validity-checking unit is coupled to the page-table register unit for checking whether the address data stored in the page table in the page-table register unit is valid or invalid.

Abstract translation: 提供了一种与SDRAM（同步动态随机存取存储器）等一起使用的存储器访问管理方法和系统，用于通过跟踪存储器访问历史来增加对SDRAM的存储器访问的性能 以前的访问操作。 存储器页管理系统包括页表寄存器单元，其包括用于存储存储器单元的预定数量的最近访问的存储器位置的页表。 此外，存储器页管理系统包括：比较单元，其能够响应于对存储器单元的每个访问请求，检查所请求的存储器位置是否是存储在页表寄存器单元中的页表中的任何一个的命中 。 利用率寄存器单元耦合到页表寄存器单元，用于监视存储在页表寄存器单元中的最近最少使用的记录; 此外，有效性检查单元耦合到页表寄存器单元，用于检查存储在页表寄存器单元中的页表中的地址数据是有效还是无效。