公开(公告)号：US08270223B2

公开(公告)日：2012-09-18

申请号：US12628710

申请日：2009-12-01

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines. A first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.

摘要翻译： 存储器件包括存储器扇区，其包括存储器扇区，一行选择晶体管和多个驱动器。 存储器扇区包括多个字线，每个字线耦合到多个存储器单元。 选择晶体管行选择存储器扇区，并将存储器扇区与存储器件中紧邻的存储器扇区分开。 多个驱动器中的每一个耦合到多个字线中的一个。 驱动器中的第一个被耦合到字线中的第一个以接收第一控制信号以传导第一字线和电压源，并且第二驱动器耦合到第二个字线 以接收第二控制信号以将第二字线与电压源断开。

公开(公告)号：US08924819B2

公开(公告)日：2014-12-30

申请号：US12358900

申请日：2009-01-23

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C29/04

CPC分类号： G06F11/1072 ,  G11C29/00 ,  G11C2029/0411

摘要： A method for operating a memory device is provided and includes the following steps. A first error correction code is generated according to user data. Then, the user data is written to the memory device. Moreover, the user data in the memory device is read, and a second error correction code is generated according to the read user data. Further, the first and the second error correction codes are written to the memory device.

摘要翻译： 提供了一种操作存储器件的方法，包括以下步骤。 根据用户数据生成第一个纠错码。 然后，将用户数据写入存储器件。 此外，读取存储器件中的用户数据，并根据读取的用户数据生成第二纠错码。 此外，将第一和第二纠错码写入存储器件。

公开(公告)号：US08363505B2

公开(公告)日：2013-01-29

申请号：US12785297

申请日：2010-05-21

申请人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Chun-Hsiung Hung

发明人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Chun-Hsiung Hung

IPC分类号： G11C8/08

CPC分类号： G11C8/08

摘要： A two transistor word line driver is disclosed. An example disclosed word line driver is simplified with common signals on the gates of the p-type and the n-type transistors. An example disclosed word line driver consumes less power by applying a negative voltage to a word line driver selected from multiple word line drivers.

摘要翻译： 公开了一种双晶体管字线驱动器。 所公开的公开的字线驱动器的示例通过p型和n型晶体管的栅极上的公共信号来简化。 所公开的字线驱动器的示例通过对从多个字线驱动器中选择的字线驱动器施加负电压而消耗较少的功率。

公开(公告)号：US20070070704A1

公开(公告)日：2007-03-29

申请号：US11552293

申请日：2006-10-24

申请人： Wen Ho ,  Yi Shih ,  Chin-Hung Chang ,  Chun-Hsiung Hung

发明人： Wen Ho ,  Yi Shih ,  Chin-Hung Chang ,  Chun-Hsiung Hung

IPC分类号： G11C11/34

CPC分类号： G11C16/3468

摘要： A page mode program sequence is described that includes first and second bias applying cycles. In the first cycle, a program bias is applied to a first part of a page of memory cells, while a program verify bias is applied to, and data is sensed from, a second part of the page. In this manner, a first part of the page is programmed, while a second part of the page is verified. This operation is followed by a second bias applying cycle, in which a program bias is applied to the second part of the page, while a program verify bias is applied to, and data is sensed from, the first part of the page.

摘要翻译： 描述了包括第一和第二偏置施加周期的页面模式程序序列。 在第一周期中，程序偏差被施加到一页存储器单元的第一部分，同时程序验证偏差被施加到页面的第二部分并且从该页面的第二部分感测数据。 以这种方式，页面的第一部分被编程，而页面的第二部分被验证。 该操作之后是第二偏置施加周期，其中将程序偏置施加到页面的第二部分，同时将程序验证偏差施加到页面的第一部分并且从页面的第一部分感测数据。

公开(公告)号：US20110149675A1

公开(公告)日：2011-06-23

申请号：US12785297

申请日：2010-05-21

申请人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Chun-Hsiung Hung

发明人： Chin-Hung Chang ,  Wen-Chiao Ho ,  Chun-Hsiung Hung

IPC分类号： G11C8/08

CPC分类号： G11C8/08

摘要： A two transistor word line driver is disclosed. An example disclosed word line driver is simplified with common signals on the gates of the p-type and the n-type transistors. An example disclosed word line driver consumes less power by applying a negative voltage to a word line driver selected from multiple word line drivers.

摘要翻译： 公开了一种双晶体管字线驱动器。 所公开的公开的字线驱动器的示例通过p型和n型晶体管的栅极上的公共信号来简化。 所公开的字线驱动器的示例通过对从多个字线驱动器中选择的字线驱动器施加负电压而消耗较少的功率。

公开(公告)号：US20110128786A1

公开(公告)日：2011-06-02

申请号：US12628710

申请日：2009-12-01

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC分类号： G11C16/14 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16

摘要： A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines, wherein a first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.

摘要翻译： 存储器件包括存储器扇区，其包括存储器扇区，一行选择晶体管和多个驱动器。 存储器扇区包括多个字线，每个字线耦合到多个存储器单元。 选择晶体管行选择存储器扇区，并将存储器扇区与存储器件中紧邻的存储器扇区分开。 多个驱动器中的每一个耦合到多个字线中的一个，其中驱动器中的第一个耦合到字线中的第一个，以接收第一控制信号以传导第一字线和电压源 并且驱动器中的第二个耦合到第二个字线以接收第二控制信号以将第二字线与电压源断开。

公开(公告)号：US20100192039A1

公开(公告)日：2010-07-29

申请号：US12358900

申请日：2009-01-23

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC分类号： H03M13/29 ,  G06F11/10

CPC分类号： G06F11/1072 ,  G11C29/00 ,  G11C2029/0411

摘要： A method for operating a memory device is provided and includes the following steps. A first error correction code is generated according to user data. Then, the user data is written to the memory device. Moreover, the user data in the memory device is read, and a second error correction code is generated according to the read user data. Further, the first and the second error correction codes are written to the memory device.

摘要翻译： 提供了一种操作存储器件的方法，包括以下步骤。 根据用户数据生成第一个纠错码。 然后，将用户数据写入存储器件。 此外，读取存储器件中的用户数据，并根据读取的用户数据生成第二纠错码。 此外，将第一和第二纠错码写入存储器件。

公开(公告)号：US06868009B1

公开(公告)日：2005-03-15

申请号：US10726124

申请日：2003-12-02

申请人： Chun-Hsiung Hung ,  Chin-Hung Chang

发明人： Chun-Hsiung Hung ,  Chin-Hung Chang

IPC分类号： G11C16/16 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/344 ,  G11C16/16

摘要： A process and a memory architecture is based on “vertical” pages, and support byte by byte erasure. A byte within a “vertical” page is erased, and then other bytes within the “vertical” page sharing bit lines with the erased byte, are subjected to a program verify operation after exposure to the stress caused by the erase process. The other bytes in the page are re-programmed to recover the data if they fail verify. Therefore, byte erase is executed without the erase/re-program cycling, and only memory cells within the same vertical page as the erased byte, which suffer stress from the erase potentials on the shared bit lines sufficient to shift their thresholds out of range, are re-programmed.

摘要翻译： 一个进程和一个内存架构是基于“垂直”页面，并支持逐字节擦除。 “垂直”页面中的字节被擦除，然后在暴露于由擦除处理引起的应力之后，在具有擦除字节的“垂直”页面共享位线中的其他字节经受编程验证操作。 页面中的其他字节被重新编程，以便在验证失败时恢复数据。 因此，在没有擦除/重新编程循环的情况下执行字节擦除，并且只有与被擦除的字节相同的垂直页面内的存储单元从共享位线上的擦除电位受到足以使其阈值超出范围的应力， 被重新编程。

公开(公告)号：US07727975B2

公开(公告)日：2010-06-01

申请号：US11983142

申请日：2007-11-07

申请人： Wei-Hsien Chang ,  Jiing-Yang Wu ,  Chin-Hung Chang ,  Yi-Shan Cheng

发明人： Wei-Hsien Chang ,  Jiing-Yang Wu ,  Chin-Hung Chang ,  Yi-Shan Cheng

IPC分类号： A61K31/718 ,  A61K31/732 ,  A61K31/738

CPC分类号： A23L29/231 ,  A23L29/219

摘要： This invention relates to a pectin-modified resistant starch prepared by cross-linking starch with pectin by pectinesterase reaction. Such resistant starch is low amylase digestible and thus is useful in food products, including nutritional supplements, to reduce calorie content and increase fiber content. This invention also relates to a composition containing the resistant starch and a process for the preparation of the same.

摘要翻译： 本发明涉及通过果胶转化酶反应将淀粉与果胶交联制备的果胶改性的抗性淀粉。 这种抗性淀粉是低淀粉酶可消化的，因此可用于食品中，包括营养补充剂，以减少卡路里含量和增加纤维含量。 本发明还涉及含有抗性淀粉的组合物及其制备方法。

公开(公告)号：US20070237879A1

公开(公告)日：2007-10-11

申请号：US11760306

申请日：2007-06-08

申请人： Jiing-Yang Wu ,  Lin-Shynag Tzeng ,  I-Chin Wang ,  Chin-Hung Chang ,  Bao-Hung Huang

发明人： Jiing-Yang Wu ,  Lin-Shynag Tzeng ,  I-Chin Wang ,  Chin-Hung Chang ,  Bao-Hung Huang

IPC分类号： A23L1/168

CPC分类号： A23L7/143

摘要： A reconstituted grain product and manufacture method thereof. The reconstituted grain product includes a ground material having a plurality of raw whole grain. The method for manufacturing a reconstituted grain product includes providing a plurality of raw materials having whole grains, grinding the raw materials to afford a ground material with between 80˜200 meshes, and subjecting the ground material to mixing, extrusion with water addition, forming and drying to yield a reconstituted grain product.

摘要翻译： 复原谷物产品及其制造方法。 复原谷物产品包括具有多个原始全谷物的研磨材料。 制造复原谷物的方法包括提供多种具有全谷粒的原料，研磨原料以提供80〜200目之间的研磨材料，并对研磨材料进行混合，用水添加，成型和 干燥以产生重构的谷物产品。