Power network stacked via removal for congestion reduction
    32.
    发明授权
    Power network stacked via removal for congestion reduction 失效
    电力网通过拆除堆叠,减少拥塞

    公开(公告)号:US07984397B2

    公开(公告)日:2011-07-19

    申请号:US12359091

    申请日:2009-01-23

    Abstract: A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded.

    Abstract translation: 提供一种在集成电路(IC)的电力网络中最小化电压降的同时自动减少堆叠通孔的方法。 在该方法中,可以虚拟地去除电力网络的任何可行的(即,不是连通性必需的和未占用的堆叠通孔)堆叠的通孔。 如果超过电力网络的目标电压降,则可以更新IC上至少最大电压降的严重程度。 在该更新之后,可以将一组降压改进的堆叠过孔实际返回给电力网络。 可以重复确定是否超过目标电压降的步骤,更新一个或多个热点处的电压降的严重性,以及实际返回该组附加堆叠通孔的步骤,直到不超过目标电压降。

    Three-dimensional viewing and editing of microcircuit design
    33.
    发明申请
    Three-dimensional viewing and editing of microcircuit design 审中-公开
    三维查看和编辑微电路设计

    公开(公告)号:US20060076547A1

    公开(公告)日:2006-04-13

    申请号:US11236424

    申请日:2005-09-26

    CPC classification number: G06F17/5068

    Abstract: An editing tool that provides a user interface for displaying and editing a representation of a microcircuit design. More particularly, the user interface displays a three dimensional representation of a second portion of the circuit design. A user can then select and edit a structure employing the three-dimensional representation of the structure in the user interface.

    Abstract translation: 一种编辑工具,提供用于显示和编辑微电路设计表示的用户界面。 更具体地,用户界面显示电路设计的第二部分的三维表示。 然后,用户可以选择和编辑采用用户界面中的结构的三维表示的结构。

    Biochip detection system
    34.
    发明申请
    Biochip detection system 失效
    生物芯片检测系统

    公开(公告)号:US20050110998A1

    公开(公告)日:2005-05-26

    申请号:US10866747

    申请日:2004-06-15

    Abstract: The present invention discloses a biochip detection system for detecting a biochip labeled with multiple fluorophores. The biochip detection system comprises a broadband light source for generating a light beam, a stand for supporting the biochip, a light integrator positioned between the broadband light source and the biochip, a lens set for adjusting the cross-sectional area of the light beam, a first filter module positioned on the optical path of the light beam, a detector, e.g., CCD camera, photodiode array, for detecting a fluorescence beam emitted from the biochip, and a second filter module positioned on the optical path of the fluorescence beam. The light integrator can be a light tunnel, a lens array or a holographic diffuser for uniforming the intensity distribution of the light beam and changing the cross-sectional shape of the light beam into a rectangle.

    Abstract translation: 本发明公开了一种用于检测用多种荧光团标记的生物芯片的生物芯片检测系统。 生物芯片检测系统包括用于产生光束的宽带光源,用于支撑生物芯片的支架,位于宽带光源和生物芯片之间的光积分器,用于调节光束横截面积的透镜组, 定位在光束的光路上的第一滤光器模块,用于检测从生物芯片发射的荧光束的CCD相机,光电二极管阵列的检测器和位于荧光束的光路上的第二滤光器模块。 光积分器可以是光通道,透镜阵列或全息漫射器,用于使光束的强度分布均匀并将光束的横截面形状改变成矩形。

    Process of implementing low frequency of audio signal
    36.
    发明申请
    Process of implementing low frequency of audio signal 审中-公开
    实现低频音频信号的过程

    公开(公告)号:US20070140511A1

    公开(公告)日:2007-06-21

    申请号:US11521751

    申请日:2006-09-15

    Abstract: A process of implementing a low frequency of an audio signal includes the steps of collecting a fundamental frequency from the audio signal at a low frequency region thereof, generating a controlled 2nd harmonic, a controlled 3rd harmonic, and a controlled 4th harmonics respectively based on a 2nd harmonic, a 3rd harmonic, and a 4th harmonic in responsive to the fundamental frequency, and generating a final output signal from a combination of the controlled 2nd harmonic, the controlled 3rd harmonic, and the controlled 4th harmonic. In which, the output signal is generated correlating with a loudness of the fundamental frequency to enhance the bass performance of an audio system device.

    Abstract translation: 实现音频信号的低频的处理包括以下步骤:从其低频区域的音频信号中收集基频,产生受控的2次谐波,受控的3 < 基于二次谐波,三次谐波和四次谐波,分别调谐谐波和受控的第四谐波。 响应于基频的次谐波,以及从被控制的第二谐波谐波的组合产生最终的输出信号,控制的第三个/ 谐波和受控的第4次谐波。 其中,产生与基频响度相关的输出信号,以增强音响系统装置的低音性能。

    Lumbar Interbody Fusion Cage for Treating Lumbar Spondylolisthesis via Lateral Approach

    公开(公告)号:US20180360614A1

    公开(公告)日:2018-12-20

    申请号:US15937868

    申请日:2018-03-28

    Abstract: The disclosure claims a lumbar interbody fusion cage for treating lumbar spondylolisthesis via a lateral approach. The lumbar interbody fusion cage comprises a supporting frame body, wherein upper and lower blades are mounted on the upper and lower end surfaces of the supporting frame body, a distracting component for driving the upper and lower blades to axially distract along a lumbar interbody and an orthotopic moving component for driving the upper and lower blades to move along the lumbar interbody back and forth are mounted in the supporting frame body, the upper and lower blades respectively extend to form lateral lobes, fixing holes through which fixing nails penetrate are formed on the lateral lobes, the fixing nail of the upper lateral lobe penetrates backward from bottom to top in a slanting way to give a certain rear thrust to the slipped lumbar vertebrae and help reduction of the lumbar spondylolisthesis, and the fixing nailing of the lower lateral lobe penetrates forward from top to bottom to give a forward thrust to the lumbar vertebrae and help the reduction of the lumbar spondylolisthesis. The lumbar interbody fusion cage can solve both an intervertebral spacing and dislocation arisen from forward and backward lumbar spondylolisthesis, has easy operation and small pain to patients, and is safer and more reliable.

    Timing variation aware compilation
    38.
    发明授权
    Timing variation aware compilation 有权
    定时变异意识编译

    公开(公告)号:US07469394B1

    公开(公告)日:2008-12-23

    申请号:US11502320

    申请日:2006-08-09

    CPC classification number: G06F8/41

    Abstract: Design compilation software uses statistical analysis techniques to account for variations in device attributes. A compilation phase determines statistical attributes of edges and other elements of device, such as the mean and variance values of attributes. A compilation phase evaluates the suitability of a potential configuration of the device using a cost function. The cost function can be based on one or more independent criteria of the design, such wiring or routing costs, timing costs, and power consumption costs. The compilation phase can include clustering, placement, and routing of the design. One or more of the cost function criteria can include statistical attributes of the device. The compilation software can use statistical attributes of the device to predict device yields for a design. The compilation software can also predict device yields of a design using devices of different speed bin classifications.

    Abstract translation: 设计编译软件使用统计分析技术来解释设备属性的变化。 汇编阶段确定设备边缘和其他元素的统计属性,如属性的均值和方差值。 编译阶段使用成本函数来评估设备的潜在配置的适用性。 成本函数可以基于设计的一个或多个独立标准,例如布线或布线成本,定时成本和功耗成本。 编译阶段可以包括设计的聚类,布局和布线。 一个或多个成本函数标准可以包括设备的统计属性。 编译软件可以使用设备的统计属性来预测设计的设备收益。 编译软件还可以使用不同速度仓分类的设备来预测设计的产量。

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