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    Method, apparatus and system for accessing remote files
    4.
    发明授权
    Method, apparatus and system for accessing remote files 有权
    用于访问远程文件的方法，设备和系统

    公开(公告)号：US08874625B2

    公开(公告)日：2014-10-28

    申请号：US13204669

    申请日：2011-08-06

    Applicant: Yan Lin ,  Chuming Chen

    Inventor： Yan Lin ,  Chuming Chen

    IPC: G06F17/30 ,  H04L29/08 ,  G06F21/62 ,  H04L29/06

    CPC classification number: H04L63/102 ,  G06F17/30203 ,  G06F21/6218 ,  G06F2221/2107 ,  H04L67/06 ,  H04L2463/101

    Abstract: The present invention relates to a method, apparatus and system for accessing remote files, wherein the method for accessing remote files comprising the following steps: obtaining download operation information for downloading a file in an operational system server; redirecting the download operation to a file server with safety space; saving a real copy of the downloaded file in the safety space and enumerating a corresponding virtual copy in the safety space. In the present invention, local file operations are redirected to the network file operations of network file storage system by redirecting the download operation on the file in the operational system server to the file server instead of being saved in the local user terminal to realize the “Not to local” effect for the key file. Even when it is power-off and then restarted, the data will not be saved in the local user terminal to achieve an effect close to “physical-like isolation”, which solves the safety problems of the offline key file much better.

    Abstract translation: 本发明涉及用于访问远程文件的方法，装置和系统，其中用于访问远程文件的方法包括以下步骤：获得用于在操作系统服务器中下载文件的下载操作信息; 将下载操作重定向到具有安全空间的文件服务器; 在安全空间中保存下载文件的真实副本，并在安全空间中枚举相应的虚拟副本。 在本发明中，通过将操作系统服务器中的文件的下载操作重定向到文件服务器而将本地文件操作重定向到网络文件存储系统的网络文件操作，而不是保存在本地用户终端中，以实现“ 不到本地“效果的关键文件。 即使电源关闭然后重新启动，数据也不会保存在本地用户终端，以达到接近“物理隔离”的效果，从而更好地解决了脱机密钥文件的安全问题。

    Power Network Stacked Via Removal For Congestion Reduction
    5.
    发明申请
    Power Network Stacked Via Removal For Congestion Reduction 失效
    通过去除堵塞电力网络来减少拥塞

    公开(公告)号：US20100190277A1

    公开(公告)日：2010-07-29

    申请号：US12359091

    申请日：2009-01-23

    Applicant: Yan Lin ,  Yi-Min Jiang ,  Lin Yuan

    Inventor： Yan Lin ,  Yi-Min Jiang ,  Lin Yuan

    IPC: H01L21/66 ,  G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/78 ,  Y02E60/76 ,  Y04S40/22

    Abstract: A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded.

    Abstract translation: 提供一种在集成电路（IC）的电力网络中最小化电压降的同时自动减少堆叠通孔的方法。 在该方法中，可以虚拟地去除电力网络的任何可行的（即，不是连通性必需的和未占用的堆叠通孔）堆叠的通孔。 如果超过电力网络的目标电压降，则可以更新IC上至少最大电压降的严重程度。 在该更新之后，可以将一组降压改进的堆叠过孔实际返回给电力网络。 可以重复确定是否超过目标电压降的步骤，更新一个或多个热点处的电压降的严重性，以及实际返回该组附加堆叠通孔的步骤，直到不超过目标电压降。

    Elastic assembly floor plan design tool
    6.
    发明申请
    Elastic assembly floor plan design tool 审中-公开
    弹性装配平面图设计工具

    公开(公告)号：US20050172252A1

    公开(公告)日：2005-08-04

    申请号：US10979868

    申请日：2004-11-01

    Applicant: Chih-Liang Cheng ,  Chung-Do Yang ,  Yan Lin ,  Kuo-Feng Liao

    Inventor： Chih-Liang Cheng ,  Chung-Do Yang ,  Yan Lin ,  Kuo-Feng Liao

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: A tool that a user may employ to assemble the components of a circuit in a floor plan design. The tool provides a user interface that displays the placement of blocks in a floor plan design, and the routing of wires among the blocks. When the designer moves the placement of a target block, the user interface automatically moves any adjacent blocks that would impede the movement of the target block and any block that would impede a block moved in response to the movement of the target block. The user interface may also respond to movement of a target block by showing how various features of the circuit will change as a result of the move. Thus, the user interface may show that moving one block closer to another block will create undesired wiring congestion in the circuit. The user interface also may show when moving a block will result in wiring connections that are too long to maintain a desired voltage level. The tool may also automatically move the placement of related blocks as a group, so that various attributes, such as a minimum distance between adjacent blocks, are maintained.

    Abstract translation: 用户可以采用的工具，用于在平面图设计中组装电路的部件。 该工具提供了一个用户界面，用于在平面图设计中显示块的位置，并在块之间布线。 当设计者移动目标块的放置时，用户界面自动地移动任何相邻的块，其将阻碍目标块的移动，并且阻止块响应于目标块的移动而移动的块。 用户接口还可以通过显示电路的各种特征如何随着移动的结果而改变而对目标块的移动做出响应。 因此，用户接口可以示出移动一个块更靠近另一个块将在电路中产生不期望的布线拥塞。 当移动块时，用户界面也可能会显示导线连接太长而不能保持所需的电压电平。 工具还可以自动地将相关块的放置移动为一组，使得保持各种属性，例如相邻块之间的最小距离。

    Power network stacked via removal for congestion reduction
    8.
    发明授权
    Power network stacked via removal for congestion reduction 失效
    电力网通过拆除堆叠，减少拥塞

    公开(公告)号：US07984397B2

    公开(公告)日：2011-07-19

    申请号：US12359091

    申请日：2009-01-23

    Applicant: Yan Lin ,  Yi-Min Jiang ,  Lin Yuan

    Inventor： Yan Lin ,  Yi-Min Jiang ,  Lin Yuan

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/78 ,  Y02E60/76 ,  Y04S40/22

    Abstract: A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded.

    Abstract translation: 提供一种在集成电路（IC）的电力网络中最小化电压降的同时自动减少堆叠通孔的方法。 在该方法中，可以虚拟地去除电力网络的任何可行的（即，不是连通性必需的和未占用的堆叠通孔）堆叠的通孔。 如果超过电力网络的目标电压降，则可以更新IC上至少最大电压降的严重程度。 在该更新之后，可以将一组降压改进的堆叠过孔实际返回给电力网络。 可以重复确定是否超过目标电压降的步骤，更新一个或多个热点处的电压降的严重性，以及实际返回该组附加堆叠通孔的步骤，直到不超过目标电压降。

    Three-dimensional viewing and editing of microcircuit design
    9.
    发明申请
    Three-dimensional viewing and editing of microcircuit design 审中-公开
    三维查看和编辑微电路设计

    公开(公告)号：US20060076547A1

    公开(公告)日：2006-04-13

    申请号：US11236424

    申请日：2005-09-26

    Applicant: Yan Lin ,  Tsubomi Imamura

    Inventor： Yan Lin ,  Tsubomi Imamura

    IPC: H01L47/00 ,  H01L29/00

    CPC classification number: G06F17/5068

    Abstract: An editing tool that provides a user interface for displaying and editing a representation of a microcircuit design. More particularly, the user interface displays a three dimensional representation of a second portion of the circuit design. A user can then select and edit a structure employing the three-dimensional representation of the structure in the user interface.

    Abstract translation: 一种编辑工具，提供用于显示和编辑微电路设计表示的用户界面。 更具体地，用户界面显示电路设计的第二部分的三维表示。 然后，用户可以选择和编辑采用用户界面中的结构的三维表示的结构。

    Biochip detection system
    10.
    发明申请
    Biochip detection system 失效
    生物芯片检测系统

    公开(公告)号：US20050110998A1

    公开(公告)日：2005-05-26

    申请号：US10866747

    申请日：2004-06-15

    Applicant: Yan Lin ,  Teh Tao ,  Zu Chow ,  Ding Liu

    Inventor： Yan Lin ,  Teh Tao ,  Zu Chow ,  Ding Liu

    IPC: G01N21/64

    CPC classification number: G01N21/6428 ,  G01N21/6456 ,  G01N2021/6419 ,  G01N2021/6441 ,  G01N2201/0631

    Abstract: The present invention discloses a biochip detection system for detecting a biochip labeled with multiple fluorophores. The biochip detection system comprises a broadband light source for generating a light beam, a stand for supporting the biochip, a light integrator positioned between the broadband light source and the biochip, a lens set for adjusting the cross-sectional area of the light beam, a first filter module positioned on the optical path of the light beam, a detector, e.g., CCD camera, photodiode array, for detecting a fluorescence beam emitted from the biochip, and a second filter module positioned on the optical path of the fluorescence beam. The light integrator can be a light tunnel, a lens array or a holographic diffuser for uniforming the intensity distribution of the light beam and changing the cross-sectional shape of the light beam into a rectangle.

    Abstract translation: 本发明公开了一种用于检测用多种荧光团标记的生物芯片的生物芯片检测系统。 生物芯片检测系统包括用于产生光束的宽带光源，用于支撑生物芯片的支架，位于宽带光源和生物芯片之间的光积分器，用于调节光束横截面积的透镜组， 定位在光束的光路上的第一滤光器模块，用于检测从生物芯片发射的荧光束的CCD相机，光电二极管阵列的检测器和位于荧光束的光路上的第二滤光器模块。 光积分器可以是光通道，透镜阵列或全息漫射器，用于使光束的强度分布均匀并将光束的横截面形状改变成矩形。

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