公开(公告)号：US20090285235A1

公开(公告)日：2009-11-19

申请号：US12120082

申请日：2008-05-13

Applicant: Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

Inventor： Kaushik Kuila ,  David T. Hass ,  Ahmed Shahid

IPC: H04J3/24

CPC classification number: H04L49/901 ,  H04L49/9021 ,  H04L49/9042 ,  H04L69/02 ,  H04L69/22 ,  H04L69/26

Abstract: A method is provided for offloading packet protocol encapsulation from software. In operation, pointer information is received. Furthermore, packet protocol encapsulation is offloaded from software by assembling packets in hardware, using the pointer information.

Abstract translation: 提供了一种从软件中卸载数据包协议封装的方法。 在操作中，接收指针信息。 此外，使用指针信息，通过在硬件中组装分组，从软件卸载分组协议封装。

公开(公告)号：US20090055496A1

公开(公告)日：2009-02-26

申请号：US12261808

申请日：2008-10-30

Applicant: Gaurav Garg ,  David T. Hass

Inventor： Gaurav Garg ,  David T. Hass

IPC: G06F15/16

CPC classification number: H04L47/10 ,  G06F12/0813 ,  H04L47/39

Abstract: A system, method, and computer program product are provided for optimal packet flow in a multi-processor system on a chip. In operation, a credit is allocated for each of a plurality of agents coupled to a messaging network, the allocating including reserving one or more entries in a receive queue of at least one of the plurality of agents. Additionally, a first credit is decremented in response to a first agent sending a message to a second agent, the plurality of agents including the first and second agents. Furthermore, one of the first credit or a second credit is incremented in response to a signal from the second agent.

Abstract translation: 提供了一种系统，方法和计算机程序产品，用于在芯片上的多处理器系统中实现最佳分组流。 在操作中，为耦合到消息收发网络的多个代理中的每个代理分配信贷，分配包括在多个代理中的至少一个代理的接收队列中保留一个或多个条目。 另外，响应于第一代理向第二代理发送消息而减少第一信用，所述多个代理包括第一和第二代理。 此外，响应于来自第二代理的信号，第一信用或第二抵免额中的一个被递增。

公开(公告)号：US07461215B2

公开(公告)日：2008-12-02

申请号：US10930187

申请日：2004-08-31

Applicant: David T. Hass

Inventor： David T. Hass

IPC: G06F12/00 ,  G06F15/16

CPC classification number: H04L47/624 ,  H04L47/24 ,  H04L47/50 ,  H04L47/568 ,  H04L49/90 ,  H04L49/9094

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US09092360B2

公开(公告)日：2015-07-28

申请号：US13195785

申请日：2011-08-01

Applicant: David T. Hass ,  Basab Mukherjee

Inventor： David T. Hass ,  Basab Mukherjee

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/10 ,  H04L12/931 ,  G06F12/08

CPC classification number: G06F12/1036 ,  G06F12/0813 ,  H04L49/00

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US08543747B2

公开(公告)日：2013-09-24

申请号：US13253044

申请日：2011-10-04

Applicant: Julianne Jiang Zhu ,  David T. Hass

Inventor： Julianne Jiang Zhu ,  David T. Hass

IPC: G06F13/42 ,  G06F3/00 ,  G06F15/76

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20120319750A1

公开(公告)日：2012-12-20

申请号：US13163605

申请日：2011-06-17

Applicant: Julianne J. Zhu ,  David T. Hass

Inventor： Julianne J. Zhu ,  David T. Hass

IPC: H03L7/08

CPC classification number: H03L7/00

Abstract: An improved approach is described for implementing a clock management system. A multi-part phase locked loop circuit is provided to handle the different clock needs of the circuit, where each of the phase locked loops within the multi-part phase locked loop circuit may feed a clock output to one or more divider circuits. The divider circuits may be dedicated to specific components. For example, a SoC PLL may generate a clock output to a SoC divider that is dedicated to providing a clock to content address memory (CAM) components. This approach allows the clock management system to efficiently generate clock signals with variable levels of frequencies, even for complicated circuits having many different functional portions and components.

Abstract translation: 描述了一种用于实现时钟管理系统的改进方法。 提供多部分锁相环电路以处理电路的不同时钟需要，其中多部分锁相环电路内的每个锁相环可以将时钟输出馈送到一个或多个除法器电路。 分频器电路可以专用于特定部件。 例如，SoC PLL可以产生时钟输出到专用于为内容地址存储器（CAM）组件提供时钟的SoC分频器。 这种方法允许时钟管理系统有效地生成具有可变电平频率的时钟信号，即使对于具有许多不同功能部分和组件的复杂电路也是如此。

公开(公告)号：US08176298B2

公开(公告)日：2012-05-08

申请号：US10930938

申请日：2004-08-31

Applicant: David T. Hass

Inventor： David T. Hass

IPC: G06F9/00

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/90

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20120089762A1

公开(公告)日：2012-04-12

申请号：US13253044

申请日：2011-10-04

Applicant: Julianne Jiang Zhu ,  David T. Hass

Inventor： Julianne Jiang Zhu ,  David T. Hass

IPC: G06F13/14

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20110225398A1

公开(公告)日：2011-09-15

申请号：US13115012

申请日：2011-05-24

Applicant: David T. Hass ,  Abbas Rashid

Inventor： David T. Hass ,  Abbas Rashid

IPC: G06F9/312

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/90

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US07991977B2

公开(公告)日：2011-08-02

申请号：US11961910

申请日：2007-12-20

Applicant: David T. Hass ,  Basab Mukherjee

Inventor： David T. Hass ,  Basab Mukherjee

IPC: G06F12/00 ,  G06F15/173

CPC classification number: G06F12/1036 ,  G06F12/0813 ,  H04L49/00

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。