公开(公告)号：US06029244A

公开(公告)日：2000-02-22

申请号：US948679

申请日：1997-10-10

申请人： Stuart Oberman ,  Norbert Juffa

发明人： Stuart Oberman ,  Norbert Juffa

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/38 ,  G06F17/16 ,  G06F9/305

CPC分类号： G06F17/16 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885

摘要： An execution unit is provided for executing a first instruction which includes an opcode field, a first operand field, and a second operand field. The execution unit includes a first input register for receiving a first operand specified by a value of the first operand field, and a second input register for receiving a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit which is coupled to receive a value of the opcode field for the first instruction. The comparator unit is also coupled to receive the first and second operand values from the first and second input registers, respectively. The execution further includes a multiplexer which receives a plurality of inputs. These inputs include a first constant value, a second constant value, and the values of the first and second operand. If the decoded opcode value received by the comparator indicates that the first instruction is either a compare or extreme value function, the comparator conveys one or more control signals to the multiplexer for the purpose of selecting an output of the multiplexer as the result of the first instruction. If the first instruction is one of a plurality of extreme value instructions, the one or more control signals conveyed by the comparator unit select between the first operand and second operand to determine the result of the first instruction. If the first instruction is one of a plurality of compare instructions, the one or more control signals conveyed by the comparator unit select between the first and second constant value to determine the result of the first instruction. In another embodiment, a similar execution unit is provided which handles vector operands.

公开(公告)号：US08589468B2

公开(公告)日：2013-11-19

申请号：US12875961

申请日：2010-09-03

申请人： Norbert Juffa ,  Radoslav Danilak

发明人： Norbert Juffa ,  Radoslav Danilak

IPC分类号： G06F7/52

CPC分类号： G06F17/16

摘要： The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs to result tiles. Yet other embodiments are methods for mapping the individual threads of a CTA to the elements of a tile for result tile computations, source tile copy operations, and source tile copy and transpose operations. The present invention advantageously enables result matrix elements to be computed on a tile-by-tile basis using multiple CTAs executing concurrently on different streaming multiprocessors, enables source tiles to be copied to local memory to reduce the number accesses from the global memory when computing a result tile, and enables coalesced read operations from the global memory as well as write operations to the local memory without bank conflicts.

摘要翻译： 本发明使得能够对并行处理装置进行有效的矩阵乘法运算。 一个实施例是用于将CTA映射到用于矩阵乘法运算的矩阵瓦片的方法。 另一个实施例是用于将CTA映射到结果瓦片的第二种方法。 其他实施例是用于将CTA的各个线程映射到块的元素以用于结果瓦片计算，源瓦片复制操作以及源瓦片复制和转置操作的方法。 本发明有利地使结果矩阵元素可以使用在不同的流式多处理器上同时执行的多个CTA来逐个瓦片地计算，使得能够将源瓦片复制到本地存储器，以减少当计算一个 结果图块，并且启用来自全局存储器的合并的读取操作以及对本地存储器的写入操作，而没有存储体冲突。

公开(公告)号：US08327123B2

公开(公告)日：2012-12-04

申请号：US13069384

申请日：2011-03-23

申请人： Norbert Juffa ,  Brett W. Coon

发明人： Norbert Juffa ,  Brett W. Coon

IPC分类号： G06F9/30

CPC分类号： G06F9/3887 ,  G06F9/3455 ,  G06F9/3851 ,  G06F9/3889

摘要： In parallel processing devices, for streaming computations, processing of each data element of the stream may not be computationally intensive and thus processing may take relatively small amounts of time to compute as compared to memory accesses times required to read the stream and write the results. Therefore, memory throughput often limits the performance of the streaming computation. Generally stated, provided are methods for achieving improved, optimized, or ultimately, maximized memory throughput in such memory-throughput-limited streaming computations. Streaming computation performance is maximized by improving the aggregate memory throughput across the plurality of processing elements and threads. High aggregate memory throughput is achieved by balancing processing loads between threads and groups of threads and a hardware memory interface coupled to the parallel processing devices.

摘要翻译： 在用于流计算的并行处理装置中，流的每个数据元素的处理可能不是计算密集的，因此与读取流并写入结果所需的存储器访问时间相比，处理可能需要相对较少的时间来计算。 因此，内存吞吐量通常会限制流计算的性能。 一般来说，提供了用于在这种存储器吞吐量限制的流计算中实现改进的，优化的或最终最大化的存储器吞吐量的方法。 通过提高跨多个处理元件和线程的聚合内存吞吐量，最大化流计算性能。 通过平衡线程和线程组之间的处理负载以及耦合到并行处理设备的硬件存储器接口来实现高聚合内存吞吐量。

公开(公告)号：US20110173414A1

公开(公告)日：2011-07-14

申请号：US13069384

申请日：2011-03-23

申请人： Norbert Juffa ,  Brett W. Coon

发明人： Norbert Juffa ,  Brett W. Coon

IPC分类号： G06F9/38

CPC分类号： G06F9/3887 ,  G06F9/3455 ,  G06F9/3851 ,  G06F9/3889

摘要： In parallel processing devices, for streaming computations, processing of each data element of the stream may not be computationally intensive and thus processing may take relatively small amounts of time to compute as compared to memory accesses times required to read the stream and write the results. Therefore, memory throughput often limits the performance of the streaming computation. Generally stated, provided are methods for achieving improved, optimized, or ultimately, maximized memory throughput in such memory-throughput-limited streaming computations. Streaming computation performance is maximized by improving the aggregate memory throughput across the plurality of processing elements and threads. High aggregate memory throughput is achieved by balancing processing loads between threads and groups of threads and a hardware memory interface coupled to the parallel processing devices.

摘要翻译： 在用于流计算的并行处理装置中，流的每个数据元素的处理可能不是计算密集的，因此与读取流并写入结果所需的存储器访问时间相比，处理可能需要相对较少的时间来计算。 因此，内存吞吐量通常会限制流计算的性能。 一般来说，提供了用于在这种存储器吞吐量限制的流计算中实现改进的，优化的或最终最大化的存储器吞吐量的方法。 通过提高跨多个处理元件和线程的聚合内存吞吐量，最大化流计算性能。 通过平衡线程和线程组之间的处理负载以及耦合到并行处理设备的硬件存储器接口来实现高聚合内存吞吐量。

公开(公告)号：US06408379B1

公开(公告)日：2002-06-18

申请号：US09329718

申请日：1999-06-10

申请人： Norbert Juffa ,  Stephan Meier ,  Stuart Oberman ,  Scott White

发明人： Norbert Juffa ,  Stephan Meier ,  Stuart Oberman ,  Scott White

IPC分类号： G06F738

CPC分类号： G06F9/3861 ,  G06F7/483 ,  G06F7/49905 ,  G06F7/4991 ,  G06F9/30014

摘要： An apparatus and method for executing floating-point store instructions in a microprocessor is provided. If store data of a floating-point store instruction corresponds to a tiny number and an underflow exception is masked, then a trap routine can be executed to generate corrected store data and complete the store operation. In response to detecting that store data corresponds to a tiny number and the underflow exception is masked, the store data, store address information, and opcode information can be stored prior to initiating the trap routine. The trap routine can be configured to access the store data, store address information, and opcode information. The trap routine can be configured to generate corrected store data and complete the store operation using the store data, store address information, and opcode information.

摘要翻译： 提供了一种用于在微处理器中执行浮点存储指令的装置和方法。 如果浮点存储指令的存储数据对应于微数，并且下溢异常被屏蔽，则可以执行陷阱例程以生成校正的存储数据并完成存储操作。 响应于检测到存储数据对应于微小数字并且下溢异常被屏蔽，可以在启动陷阱例程之前存储存储数据，存储地址信息和操作码信息。 陷阱程序可以配置为访问存储数据，存储地址信息和操作码信息。 陷阱程序可以配置为生成更正的存储数据，并使用存储数据，存储地址信息和操作码信息完成存储操作。

公开(公告)号：US06256653B1

公开(公告)日：2001-07-03

申请号：US09015084

申请日：1998-01-29

申请人： Norbert Juffa ,  Stuart F. Oberman

发明人： Norbert Juffa ,  Stuart F. Oberman

IPC分类号： G06F102

CPC分类号： G06F7/53 ,  G06F7/483 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/49963 ,  G06F7/49994 ,  G06F7/509 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885 ,  G06F17/16 ,  G06F2207/3828 ,  H03M7/24

摘要： A multi-function look-up table for determining output values for predetermined ranges of a first mathematical function and a second mathematical function. In one embodiment, the multi-function look-up table is a bipartite look-up table including a first plurality of storage locations and a second plurality of storage locations. The first plurality of storage locations store base values for the first and second mathematical functions. Each base value is an output value (for either the first or second function) corresponding to an input region which includes the look-up table input value. The second plurality of storage locations, on the other hand, store difference values for both the first and second mathematical functions. These difference values are used for linear interpolation in conjunction with a corresponding base value in order to generate a look-up table output value. The multi-function look-up table further includes an address control unit coupled to receive a first input value and a signal which indicates whether an output value is to be generated for the first or second mathematical function. The address control unit then generates a first address value from these signals which is in turn conveyed to the first and second plurality of storage locations. In response to receiving the first address value, the first and second plurality of storage locations are configured to output a first base value and a first difference value, respectively. The first base value and first difference value are then conveyed to an output unit configured to generate a look-up table output value from the two values.

摘要翻译： 一种用于确定第一数学函数和第二数学函数的预定范围的输出值的多功能查找表。 在一个实施例中，多功能查找表是包括第一多个存储位置和第二多个存储位置的二分查找表。 第一多个存储位置存储第一和第二数学函数的基值。 每个基值是对应于包括查找表输入值的输入区域的输出值（对于第一或第二函数）。 另一方面，第二多个存储位置存储第一和第二数学函数的差值。 这些差值用于与对应的基值相结合的线性插值，以产生查询表输出值。 多功能查找表还包括地址控制单元，其被耦合以接收第一输入值和指示是否为第一或第二数学函数生成输出值的信号。 地址控制单元然后从这些信号产生一个第一地址值，该第一地址值又被传送到第一和第二多个存储位置。 响应于接收到第一地址值，第一和第二多个存储位置被配置为分别输出第一基值和第一差值。 然后将第一基值和第一差分值传送到被配置为从两个值生成查找表输出值的输出单元。

公开(公告)号：US06223198B1

公开(公告)日：2001-04-24

申请号：US09134171

申请日：1998-08-14

申请人： Stuart Oberman ,  Norbert Juffa ,  Ming Siu ,  Frederick D Weber ,  Ravikrishna Cherukuri

发明人： Stuart Oberman ,  Norbert Juffa ,  Ming Siu ,  Frederick D Weber ,  Ravikrishna Cherukuri

IPC分类号： G06F752

CPC分类号： G06F7/53 ,  G06F7/4991 ,  G06F7/49936 ,  G06F7/49963 ,  G06F7/49994 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/30036 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885 ,  G06F17/16 ,  G06F2207/3828

摘要： A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines. The segments may be rounded by adding a rounding constant. Rounding and normalization may be performed in two paths, one assuming an overflow will occur, the other assuming no overflow will occur. The multiplier may also be configured to perform iterative calculations to evaluate constant powers of an operand. Intermediate products that are formed may be rounded and normalized in two paths and then compressed and stored for use in the next iteration. An adjustment constant may also be added to increase the frequency of exactly rounded results.