公开(公告)号：US20090289288A1

公开(公告)日：2009-11-26

申请号：US12126102

申请日：2008-05-23

申请人： Dongping Wu

发明人： Dongping Wu

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10855 ,  H01L27/10867 ,  H01L27/10873 ,  H01L29/1083

摘要： An integrated circuit including an insulating structure below a source/drain region and a method. One embodiment includes a memory cell with an access transistor and a storage element. A first source/drain region of the access transistor is electrically coupled to the storage element. A first insulating structure is disposed between the first source/drain region and a first portion of a semiconductor substrate, the first portion being arranged below the first source/drain region. A channel region of the access transistor is formed between the first and a second source/drain region of the access transistor in an active area being electrically coupled to the first portion of the semiconductor substrate.

摘要翻译： 一种包括源极/漏极区域下方的绝缘结构的集成电路和方法。 一个实施例包括具有存取晶体管和存储元件的存储单元。 存取晶体管的第一源/漏区电耦合到存储元件。 第一绝缘结构设置在第一源极/漏极区域和半导体衬底的第一部分之间，第一部分布置在第一源极/漏极区域下方。 存取晶体管的沟道区形成在与半导体衬底的第一部分电耦合的有源区中的存取晶体管的第一和第二源极/漏极区之间。

公开(公告)号：US20080012067A1

公开(公告)日：2008-01-17

申请号：US11486385

申请日：2006-07-14

申请人： Dongping Wu

发明人： Dongping Wu

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/66621 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/7851

摘要： A method of forming a transistor involves defining an active area by defining isolation trenches, the isolation trenches being adjacent to the active area, and forming a gate electrode after defining the isolation trenches. The gate electrode is formed by etching a gate groove in the active area selectively with respect to an insulating material filling the isolation trenches, etching the insulating material filling the isolation trenches at a portion adjacent to a channel such that a portion of the channel having the shape of a ridge with a top side and two lateral sides is uncovered, providing a gate insulating material on the top side and the lateral sides, and providing a conducting material on the gate insulating layer such that the gate electrode is disposed along the top side and the two lateral sides of the channel.

摘要翻译： 形成晶体管的方法包括通过限定隔离沟槽来限定有源区域，隔离沟槽与有源区域相邻，以及在限定隔离沟槽之后形成栅电极。 通过相对于填充隔离沟槽的绝缘材料选择性地蚀刻有源区中的栅极沟槽来蚀刻栅电极，蚀刻在与沟道相邻的部分处填充隔离沟槽的绝缘材料，使得沟道的一部分具有 具有顶侧和两侧面的脊的形状未被覆盖，在顶侧和侧面上提供栅极绝缘材料，并且在栅绝缘层上提供导电材料，使得栅电极沿着顶侧 和通道的两个侧面。

公开(公告)号：US20070015325A1

公开(公告)日：2007-01-18

申请号：US11183224

申请日：2005-07-14

申请人： Matthias Goldbach ,  Dongping Wu

发明人： Matthias Goldbach ,  Dongping Wu

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857

摘要： The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The manufacturing method comprises the steps of: providing a semiconductor substrate (1) having an upper surface (O) and having first and second transistor regions (T1, T2); wherein said first transistor region (T1) is a n-MOSFET region and second transistor region (T2) is a p-MOSFET region; forming a gate structure on said first and second transistor region (T1, T2) including at least one gate dielectric layer (2, 3, 10c, 17, 25) and one gate layer (4; 35; 50, 60) in each of said first and second transistor regions (T1, T2); wherein said gate layer (4; 35; 60) in said second transistor region (T2) is made of negatively doped polysilicon; wherein said at least one gate dielectric layer (2, 10c, 17) in said first transistor region (T1) comprises a first dielectric layer (2, 10c, 17); wherein said at least one gate dielectric layer (2, 3, 10c, 25, 25′) in said second transistor region (T2) comprises an interfacial dielectric layer (2; 25; 25′) located adjacent to said gate layer (4; 35; 60) in said second transistor region (T2), which interfacial dielectric layer (2; 25; 25′) forms an Al2O3 containing interface on said gate layer (4; 35; 60) in said second transistor region (T2) causing a Fermi-pinning effect; and wherein said first transistor region (T1) does not include said interfacial dielectric layer (2; 25; 25′).

公开(公告)号：US20090184357A1

公开(公告)日：2009-07-23

申请号：US12016342

申请日：2008-01-18

申请人： Dongping Wu

发明人： Dongping Wu

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L21/84 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/66621

摘要： A SOI based integrated circuit and method for manufacturing a SOI based integrated circuit is disclosed. One embodiment provides an integrated circuit having a silicon-on-insulator carrier including a substrate, a buried insulating layer on the substrate and a semiconductor layer on the buried insulating layer. A trench extends at least through the semiconductor layer and into the buried insulating layer. A conductive region is formed in the buried insulating layer, wherein the conductive region partly surrounds the trench and is configured to interconnect the semiconductor layer and the substrate.

摘要翻译： 公开了一种用于制造基于SOI的集成电路的基于SOI的集成电路和方法。 一个实施例提供了一种集成电路，其具有包括衬底的绝缘体上硅载体，衬底上的掩埋绝缘层和掩埋绝缘层上的半导体层。 沟槽至少延伸穿过半导体层并进入掩埋绝缘层。 在掩埋绝缘层中形成导电区域，其中导电区域部分地围绕沟槽并且被配置为将半导体层和衬底互连。

公开(公告)号：US20060226473A1

公开(公告)日：2006-10-12

申请号：US11101378

申请日：2005-04-07

申请人： Dongping Wu ,  Matthias Goldbach ,  Ulrich Egger

发明人： Dongping Wu ,  Matthias Goldbach ,  Ulrich Egger

IPC分类号： H01L29/792

CPC分类号： H01L21/28061 ,  H01L21/2807 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/76897 ,  H01L27/10873 ,  H01L29/4941 ,  H01L29/517

摘要： A gate electrode stack is disposed on a substrate in a semiconductor device. A gate conductor includes at least one layer of polysilicon and at least one layer of poly-Si1−x,Gex material. The invention is also concerned with a process. This structure can be etched effectively since an end point detection is enabled.

摘要翻译： 栅电极堆叠设置在半导体器件中的衬底上。 栅极导体包括至少一层多晶硅和至少一层多晶Si 1-x N，Ge x S x材料。 本发明也涉及一个过程。 可以有效地蚀刻这种结构，因为启用了终点检测。

公开(公告)号：US08445351B2

公开(公告)日：2013-05-21

申请号：US13255240

申请日：2011-01-04

申请人： Dongping Wu ,  Shi-Li Zhang

发明人： Dongping Wu ,  Shi-Li Zhang

IPC分类号： H01L21/336 ,  H01L21/338 ,  H01L21/8238 ,  H01L21/425

CPC分类号： H01L27/11521

摘要： The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region of the semiconductor substrate other than regions corresponding to the source and drain. The first polysilicon layer is disposed over the first insulator layer, forming a floating gate. The second insulator layer is disposed over the first polysilicon layer. The second polysilicon layer is disposed over the second insulator layer, forming a control gate and a wordline. The sidewalls are disposed on two sides of the wordline, and the protective layer is disposed over the second polysilicon layer. A semiconductor junction at a drain region is a P-N junction, while a semiconductor junction at a source region is a metal-semiconductor junction.

摘要翻译： 本发明提供一种浮栅非易失性半导体存储器件及其制造方法。 浮栅非易失性半导体存储器件包括半导体衬底，源极，漏极，第一绝缘体层，第一多晶硅层，第二绝缘体层，第二多晶硅层，保护层和侧壁。 源极和漏极设置在半导体衬底上。 第一绝缘体层设置在除了与源极和漏极对应的区域之外的半导体衬底的区域上。 第一多晶硅层设置在第一绝缘体层上，形成浮栅。 第二绝缘体层设置在第一多晶硅层上。 第二多晶硅层设置在第二绝缘体层上，形成控制栅极和字线。 侧壁设置在字线的两侧，并且保护层设置在第二多晶硅层上。 漏极区域的半导体结是P-N结，源极区的半导体结是金属 - 半导体结。

公开(公告)号：US20120292733A1

公开(公告)日：2012-11-22

申请号：US13255501

申请日：2011-01-04

申请人： Dongping Wu ,  Shi-Li Zhang ,  Yinghua Pu

发明人： Dongping Wu ,  Shi-Li Zhang ,  Yinghua Pu

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/861 ,  H01L29/6609 ,  H01L29/66143 ,  H01L29/872

摘要： The present invention relates to the field of microelectronic technology. It discloses a mixed Schottky/P-N junction diode and a method of making the same. The mixed Schottky/P-N junction diode comprises a semiconductor substrate having a bulk region and a doped region, and a conductive layer on the semiconductor substrate. The doped region has opposite doping from that of the bulk region. A P-N junction is formed between the bulk region and the doped region, a Schottky junction is formed between the conductive layer and the semiconductor substrate, and an ohmic contact is formed between the conductive layer and the doped region. The mixed Schottky/P-N junction diode of the present invention has high operating current, fast switching speed, small leakage current, high breakdown voltage, ease of fabrication and other advantages.

摘要翻译： 本发明涉及微电子技术领域。 它公开了一种混合肖特基/ P-N结二极管及其制造方法。 混合肖特基/ P-N结二极管包括具有体区和掺杂区的半导体衬底，以及在半导体衬底上的导电层。 掺杂区域具有与本体区域相反的掺杂。 在体区和掺杂区之间形成P-N结，在导电层和半导体衬底之间形成肖特基结，在导电层和掺杂区之间形成欧姆接触。 本发明的混合肖特基/ P-N结二极管具有工作电流高，开关速度快，漏电流小，击穿电压高，制造容易等优点。

公开(公告)号：US07880210B2

公开(公告)日：2011-02-01

申请号：US12126102

申请日：2008-05-23

申请人： Dongping Wu

发明人： Dongping Wu

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10855 ,  H01L27/10867 ,  H01L27/10873 ,  H01L29/1083

摘要： An integrated circuit including an insulating structure below a source/drain region and a method. One embodiment includes a memory cell with an access transistor and a storage element. A first source/drain region of the access transistor is electrically coupled to the storage element. A first insulating structure is disposed between the first source/drain region and a first portion of a semiconductor substrate, the first portion being arranged below the first source/drain region. A channel region of the access transistor is formed between the first and a second source/drain region of the access transistor in an active area being electrically coupled to the first portion of the semiconductor substrate.

摘要翻译： 一种包括源极/漏极区域下方的绝缘结构的集成电路和方法。 一个实施例包括具有存取晶体管和存储元件的存储单元。 存取晶体管的第一源/漏区电耦合到存储元件。 第一绝缘结构设置在第一源极/漏极区域和半导体衬底的第一部分之间，第一部分布置在第一源极/漏极区域下方。 存取晶体管的沟道区形成在与半导体衬底的第一部分电耦合的有源区中的存取晶体管的第一和第二源极/漏极区之间。

公开(公告)号：US07781838B2

公开(公告)日：2010-08-24

申请号：US12106456

申请日：2008-04-21

申请人： Dongping Wu

发明人： Dongping Wu

IPC分类号： H01L27/01

CPC分类号： H01L29/7841 ,  H01L21/74 ,  H01L21/743 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/78654

摘要： An integrated circuit including a floating body transistor and method. One embodiment provides a transistor including a body region formed in a first portion and a first and a second source/drain region formed in a second and a third portion. The body region is formed in a semiconductor substrate. The integrated circuit further includes a buried structure disposed at least below the body region and a first and a second insulating structure including an insulating material and being disposed at least between the body region and regions of the second and the third portion below the first and the second source drain region, wherein the first and the second insulating structure contact the buried structure.

摘要翻译： 一种包括浮体晶体管和方法的集成电路。 一个实施例提供一种晶体管，其包括形成在第一部分中的主体区域和形成在第二和第三部分中的第一和第二源极/漏极区域。 身体区域形成在半导体衬底中。 集成电路还包括至少设置在身体区域下方的掩埋结构以及包括绝缘材料的第一和第二绝缘结构，并且至少设置在第一和第二部分之下的主体区域和第二和第三部分的区域之间。 第二源极漏极区，其中所述第一和第二绝缘结构接触所述掩埋结构。