公开(公告)号：US09076730B2

公开(公告)日：2015-07-07

申请号：US13704601

申请日：2012-12-12

申请人： Dongping Wu ,  Peng Xu ,  Wei Zhang ,  Shi-Li Zhang

发明人： Dongping Wu ,  Peng Xu ,  Wei Zhang ,  Shi-Li Zhang

IPC分类号： H01L21/285 ,  H01L29/66 ,  H01L29/786 ,  H01L21/324

CPC分类号： H01L21/28518 ,  H01L21/2855 ,  H01L21/324 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66643 ,  H01L29/66742 ,  H01L29/786

摘要： A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node.

摘要翻译： 公开了一种金属硅化物薄膜和超浅结的制造方法。 在本公开中，通过使用金属和半导体掺杂剂混合物作为靶，使用物理气相沉积（PVD）工艺在半导体衬底上形成混合膜。 然后通过湿蚀刻除去混合物膜，随后退火以形成金属硅化物薄膜和超浅结。 由于金属和半导体掺杂剂混合物用作沉积混合物膜的靶，并且在退火之前通过湿蚀刻除去混合物膜，形成自限制，超薄且均匀的金属硅化物膜和超浅结 同时在半导体场效应晶体管制造工艺中，其适用于14nm，11nm甚至更进一步的技术节点处的场效应晶体管。

公开(公告)号：US20140315366A1

公开(公告)日：2014-10-23

申请号：US13704615

申请日：2012-12-14

申请人： Dongping Wu ,  Chenyu Wen ,  Wei Zhang ,  Shi-Li Zhang

发明人： Dongping Wu ,  Chenyu Wen ,  Wei Zhang ,  Shi-Li Zhang

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/283

CPC分类号： H01L29/665 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by concurrently formed metal-semiconductor compound contact regions at the source and drain and metal-semiconductor compounds in vias formed at positions corresponding to the source and drain. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the metal-semiconductor compounds in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the metal-semiconductor compound source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias.

摘要翻译： 本公开涉及半导体技术，并公开了一种半导体器件及其制造方法。 在本公开中，晶体管的源极和漏极由在源极和漏极处形成的通孔中形成的金属 - 半导体化合物接触区域和与源极和漏极相对应的通孔中的金属 - 半导体化合物引出。 因为金属 - 半导体化合物具有相对低的电阻率，所以可以使过孔中金属 - 半导体化合物的电阻最小化。 此外，由于用于填充通孔的材料和形成源极/漏极接触区域的材料都是金属 - 半导体化合物，所以填充通孔的材料与金属 - 半导体化合物源极/漏极接触区域之间的接触电阻可以被最小化。 此外，由于填充过孔的材料是金属 - 半导体化合物，所以绝缘体层中的通孔和电介质材料中的导电材料可以形成良好的界面并且具有良好的粘合性能，并且导电材料不会在介电材料中引起结构损坏 。 因此，不需要在绝缘体层和填充通孔的材料之间形成阻挡层。

公开(公告)号：US08476154B2

公开(公告)日：2013-07-02

申请号：US13255495

申请日：2011-01-04

申请人： Dongping Wu ,  Shi-Li Zhang

发明人： Dongping Wu ,  Shi-Li Zhang

IPC分类号： H01L21/44 ,  H01L21/28 ,  H01L21/338 ,  H01L21/8238 ,  H01L21/425 ,  H01L21/265

CPC分类号： H01L27/11521 ,  H01L27/11568 ,  H01L29/792

摘要： The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.

摘要翻译： 本发明提供一种电荷俘获非易失性半导体存储器件及其制造方法。 电荷俘获非易失性半导体存储器件包括半导体衬底，源极区，漏极区，并且在半导体衬底上连续形成沟道绝缘层，电荷俘获层，阻挡绝缘层和栅电极 。 漏极区域包括P-N结，并且源区域包括在半导体衬底和包括钛，钴，镍，铂或其各种组合之类的金属之间形成的金属 - 半导体结。 根据本公开的电荷捕获非易失性半导体存储器件具有低编程电压，快速编程速度，低能量消耗和相对高的器件可靠性。

公开(公告)号：US20120119268A1

公开(公告)日：2012-05-17

申请号：US13255498

申请日：2011-01-04

申请人： Dongping Wu ,  Shi-Li Zhang ,  Liang Ge ,  Zhi-Jun Chou

发明人： Dongping Wu ,  Shi-Li Zhang ,  Liang Ge ,  Zhi-Jun Chou

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66643 ,  H01L29/7839

摘要： The present invention is related to microelectronic technologies, and discloses specifically a mixed junction source/drain field-effect-transistor and methods of making the same. The field-effect-transistor with mixed junction source/drain comprises a semiconductor substrate, a gate structure, sidewalls, and source and drain regions having mixed junction structures, which are combinations of Schottky and P-N junctions. Compared with Schottky junction field-effect-transistors, the mixed junction source/drain field-effect-transistor described in the present invention has the characteristics of relatively low source/drain leakage. At the same time, this field-effect-transistor has lower source/drain series resistances than that associated with P-N junction field-effect-transistors.

摘要翻译： 本发明涉及微电子技术，专门公开了混合结源极/漏极场效应晶体管及其制造方法。 具有混合结源极/漏极的场效应晶体管包括半导体衬底，栅极结构，侧壁以及具有混合结结构的源极和漏极区，其是肖特基和P-N结的组合。 与肖特基结场效应晶体管相比，本发明描述的混合结源极/漏极场效应晶体管具有源/漏泄漏相对较低的特性。 同时，该场效应晶体管具有比与P-N结场效应晶体管相关联的更低的源极/漏极串联电阻。

公开(公告)号：US20120267698A1

公开(公告)日：2012-10-25

申请号：US13255240

申请日：2011-01-04

申请人： Dongping Wu ,  Shi-Li Zhang

发明人： Dongping Wu ,  Shi-Li Zhang

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521

摘要： The present invention provides a floating-gate non-volatile semiconductor memory device and a method of making the same. The floating-gate non-volatile semiconductor memory device comprises a semiconductor substrate, a source, a drain, a first insulator layer, a first polysilicon layer, a second insulator layer, a second polysilicon layer, a protective layer and sidewalls. The source and drain are disposed on the semiconductor substrate. The first insulator layer is disposed over a region of the semiconductor substrate other than regions corresponding to the source and drain. The first polysilicon layer is disposed over the first insulator layer, forming a floating gate. The second insulator layer is disposed over the first polysilicon layer. The second polysilicon layer is disposed over the second insulator layer, forming a control gate and a wordline. The sidewalls are disposed on two sides of the wordline, and the protective layer is disposed over the second polysilicon layer. A semiconductor junction at a drain region is a P-N junction, while a semiconductor junction at a source region is a metal-semiconductor junction.

摘要翻译： 本发明提供一种浮栅非易失性半导体存储器件及其制造方法。 浮栅非易失性半导体存储器件包括半导体衬底，源极，漏极，第一绝缘体层，第一多晶硅层，第二绝缘体层，第二多晶硅层，保护层和侧壁。 源极和漏极设置在半导体衬底上。 第一绝缘体层设置在除了与源极和漏极对应的区域之外的半导体衬底的区域上。 第一多晶硅层设置在第一绝缘体层上，形成浮栅。 第二绝缘体层设置在第一多晶硅层上。 第二多晶硅层设置在第二绝缘体层上，形成控制栅极和字线。 侧壁设置在字线的两侧，并且保护层设置在第二多晶硅层上。 漏极区域的半导体结是P-N结，源极区的半导体结是金属 - 半导体结。

公开(公告)号：US20110316070A1

公开(公告)日：2011-12-29

申请号：US13255495

申请日：2011-01-04

申请人： Dongping Wu ,  Shi-Li Zhang

发明人： Dongping Wu ,  Shi-Li Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/11568 ,  H01L29/792

摘要： The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability.

摘要翻译： 本发明提供一种电荷俘获非易失性半导体存储器件及其制造方法。 电荷捕获非易失性半导体存储器件包括半导体衬底，源极区，漏极区，并且在半导体衬底上连续形成沟道绝缘层，电荷俘获层，阻挡绝缘层和栅电极 。 漏极区域包括P-N结，并且源区域包括在半导体衬底和包括钛，钴，镍，铂或其各种组合之类的金属之间形成的金属 - 半导体结。 根据本公开的电荷捕获非易失性半导体存储器件具有低编程电压，快速编程速度，低能量消耗和相对高的器件可靠性。

公开(公告)号：US09570595B2

公开(公告)日：2017-02-14

申请号：US13704613

申请日：2012-12-14

申请人： Dongping Wu ,  Chaochao Fu ,  Wei Zhang ,  Shi-Li Zhang

发明人： Dongping Wu ,  Chaochao Fu ,  Wei Zhang ,  Shi-Li Zhang

IPC分类号： H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/285 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/45 ,  H01L21/02

CPC分类号： H01L29/7378 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/28518 ,  H01L21/2855 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/7371

摘要： A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency performance of the SiGe HBT is significantly improved through a better thermal process budget for the base profile, essential for higher cut-off frequency (fT) and a minimal collector-base area for a reduced parasitic capacitance, essential for higher maximum oscillation frequency (fmax). This inverted heterojunction structure can be fabricated by using ALE processes to form an emitter on a preformed epitaxial silicide, a base over the emitter and a collector over the base.

摘要翻译： SiGe HBT具有反相异质结结构，其中发射极层在基极层和集电极层之前形成。 SiGe HBT的频率性能通过基底轮廓的更好的热处理预算得到显着改善，对于较高的截止频率（fT）和减少的寄生电容的最小集电极基极面积是必不可少的，因为较高的最大振荡频率 （fmax）。 该反转异质结结构可以通过使用ALE工艺在预制的外延硅化物上形成发射极，在发射极上的基极和在基极上的集电极来制造。

公开(公告)号：US20140008604A1

公开(公告)日：2014-01-09

申请号：US13502110

申请日：2011-09-28

申请人： Dongping Wu ,  Shi-Li Zhang ,  Zhiwei Zhu ,  Wei Zhang

发明人： Dongping Wu ,  Shi-Li Zhang ,  Zhiwei Zhu ,  Wei Zhang

IPC分类号： H01L29/06 ,  H01L21/308

CPC分类号： H01L29/0669 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L29/122

摘要： The present invention disclosure provides a super-long semiconductor nanowire structure. The super-long semiconductor nanowire structure is intermittently widened to prevent fractures in the super-long semiconductor nanowire structure. At the same time, the present invention further provides a method of making a super-long semiconductor nanowire structure. The method forms an intermittently widened super-long semiconductor nanowire structure using photolithography and etching. Because the super-long semiconductor nanowire structure is intermittently widened, fracturing of the super-long semiconductor nanowire structure during etching can be avoided, making it easier to form a super-long and ultra-thin semiconductor nanowire structure.

摘要翻译： 本发明公开了一种超长半导体纳米线结构。 超长半导体纳米线结构被间歇地加宽以防止超长半导体纳米线结构中的断裂。 同时，本发明还提供了制造超长半导体纳米线结构的方法。 该方法使用光刻和蚀刻形成间歇加宽的超长半导体纳米线结构。 因为超长半导体纳米线结构被间歇地加宽，所以可以避免在蚀刻过程中超长半导体纳米线结构的断裂，从而更容易形成超长和超薄的半导体纳米线结构。

公开(公告)号：US20130140625A1

公开(公告)日：2013-06-06

申请号：US13642286

申请日：2011-04-25

申请人： Yinghua Piao ,  Liang Ge ,  Dongping Wu ,  Shi-Li Zhang ,  Wei Zhang

发明人： Yinghua Piao ,  Liang Ge ,  Dongping Wu ,  Shi-Li Zhang ,  Wei Zhang

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66643 ,  H01L29/66659 ,  H01L29/7839

摘要： The present invention belongs to the field of microelectronic device technologies. Specifically, an asymmetric source/drain field-effect transistor and its methods of making are disclosed. A structure of the field-effect transistor comprises: a semiconductor substrate, a gate structure, and a source region and a drain region having a mixed junction and a P-N junction, respectively. The source region and the drain region are asymmetrical structured with respect to each other, one of which comprises a P-N junction, and the other of which comprises a mixed junction, the mixed junction being a combination of a Schottky junction and a P-N junction. According to the present disclosure, a location of a doped region formed by ion implantation is controlled by adjusting an implantation angle, and a unique structure is formed for the asymmetric source/drain field-effect transistor.

摘要翻译： 本发明属于微电子器件技术领域。 具体地说，公开了非对称源极/漏极场效应晶体管及其制造方法。 场效应晶体管的结构包括：半导体衬底，栅极结构，以及分别具有混合结和P-N结的源极区和漏极区。 源极区和漏极区彼此不对称地构成，其中之一包括P-N结，另一个包括混合结，该混合结是肖特基结和P-N结的组合。 根据本公开，通过调整注入角度来控制通过离子注入形成的掺杂区域的位置，并且为非对称源极/漏极场效应晶体管形成独特的结构。

公开(公告)号：US20130126954A1

公开(公告)日：2013-05-23

申请号：US13255503

申请日：2011-01-04

申请人： Dongping Wu ,  Shi-Li Zhang ,  Peng-Fei Wang ,  Wei Zhang

发明人： Dongping Wu ,  Shi-Li Zhang ,  Peng-Fei Wang ,  Wei Zhang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10864 ,  H01L27/10823 ,  H01L27/1087 ,  H01L27/10876 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is related to microelectronic technologies, and discloses specifically a dynamic random access memory (DRAM) array and methods of making the same. The DRAM array uses vertical MOS field effect transistors as array devices for the DRAM, and a buried metal silicide layer as buried bit lines for connecting multiple consecutive vertical MOS field effect transistor array devices. Each of the vertical MOS field-effect-transistor array devices includes a double gate structure with a buried layer of metal, which acts at the same time as buried word lines for the DRAM array. The DRAM array according to the present invention provides increased DRAM integration density, reduced buried bit line resistivity, and improved memory performance of the array devices. The present invention also provides a method of making a DRAM array.

摘要翻译： 本发明涉及微电子技术，特别公开了一种动态随机存取存储器（DRAM）阵列及其制造方法。 DRAM阵列使用垂直MOS场效应晶体管作为用于DRAM的阵列器件，并且埋入金属硅化物层作为用于连接多个连续垂直MOS场效应晶体管阵列器件的掩埋位线。 每个垂直MOS场效应晶体管阵列器件包括具有金属掩埋层的双栅结构，其与DRAM阵列的掩埋字线同时作用。 根据本发明的DRAM阵列提供增加的DRAM集成密度，降低的掩埋位线电阻率和改进的阵列器件的存储器性能。 本发明还提供了一种制造DRAM阵列的方法。