公开(公告)号：US06961921B2

公开(公告)日：2005-11-01

申请号：US10037609

申请日：2002-01-02

申请人： Edward L. Hepler ,  Michael F. Starsinic

发明人： Edward L. Hepler ,  Michael F. Starsinic

IPC分类号： G06F11/10 ,  H03M13/29 ,  H03M13/39 ,  H03M13/45 ,  H03M13/03

CPC分类号： H03M13/3905 ,  H03M13/3972 ,  H03M13/6505

摘要： The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is read from memory on the same clock edge that the new forward metric is written to the same memory location. Although this architecture was developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.

摘要翻译： 流水线最大后验（MAP）解码器架构的滑动窗口方法被修改以减少处理时间。 一旦为解码器的第一滑动窗口计算了前向量度，则在计算下一个窗口的前向量度时，计算每个窗口的反向度量。 当每个新的前向度量被计算并存储到存储器中时，从存储器中读取来自前一窗口的前向度量用于在计算外在值时计算的反向度量。 用于计算外在值的每个前向量度在相同的时钟边沿从存储器读取，该时钟边沿将新的前向量度写入相同的存储器位置。 虽然该架构是为turbo解码器开发的，但是所有的卷积码都可以使用本发明的MAP算法。

公开(公告)号：US08316285B2

公开(公告)日：2012-11-20

申请号：US13045041

申请日：2011-03-10

申请人： Edward L. Hepler ,  Michael F. Starsinic

发明人： Edward L. Hepler ,  Michael F. Starsinic

IPC分类号： H03M13/00

CPC分类号： H03M13/3905 ,  H03M13/3972 ,  H03M13/6505

摘要： Methods and apparatus for performing error correction of data bits are disclosed. A forward metric calculation may be performed during a first window to generate a first group of calculated data. The first group of calculated data from the forward calculation may be stored in a memory location. A forward metric calculation may be performed during a second window to generate a second group of calculated data. The first group of calculated data may be read from the memory location and the second group of calculated data may be stored in the same memory location. The first group of calculated data may be used to calculate reverse metrics.

摘要翻译： 公开了进行数据位纠错的方法和装置。 可以在第一窗口期间执行前向度量计算，以生成第一组计算数据。 来自正向计算的第一组计算数据可以存储在存储器位置中。 可以在第二窗口期间执行前向度量计算，以生成第二组计算数据。 可以从存储器位置读取第一组计算数据，并且将第二组计算数据存储在相同的存储单元中。 计算数据的第一组可用于计算反向度量。

公开(公告)号：US20090274248A1

公开(公告)日：2009-11-05

申请号：US12428626

申请日：2009-04-23

申请人： Edward L. Hepler ,  Geetha L. Narayan

发明人： Edward L. Hepler ,  Geetha L. Narayan

IPC分类号： H04L27/06 ,  G11C29/00

CPC分类号： H03M13/2775 ,  H03M13/2739 ,  H03M13/2764 ,  H03M13/2957 ,  H04L1/0071

摘要： A method and apparatus for contention free interleaving are disclosed. A single memory configured to use an address scheme wherein the most significant bits (MSBs) indicate which word in memory stores an interleaved piece of data. The least significant bits (LSBs) are used to calculate an index that identifies a specific soft-in/soft-out (SISO) decoder associated with a sub-word of the retrieved data. Using an interleaved address generator, the extrinsic data may be written into the memory in sequential order, but read out from the memory in interleaved order, effectively de-interleaving the data so it may be decoded. The generated interleaved address is used by SISO selector circuit which controls a multiplexer that routes the sub-word to its appropriate SISO decoder. The same address generator may be used to write interleaved extrinsic data from SISOs by reordering the sub-words, allowing the extrinsic data to be read in sequential order.

摘要翻译： 公开了一种无争用交错的方法和装置。 配置为使用地址方案的单个存储器，其中最高有效位（MSB）指示存储器中的哪个字存储交错数据段。 最低有效位（LSB）用于计算识别与检索的数据的子字相关联的特定软入/软输出（SISO）解码器的索引。 使用交错地址生成器，外部数据可以按顺序写入存储器，但是以交错顺序从存储器读出，有效地对数据进行解交织，以便其被解码。 生成的交错地址由SISO选择器电路使用，SISO选择器电路控制将子字路由到其适当的SISO解码器的多路复用器。 相同的地址生成器可以用于通过重新排序子字来从SISO写入交错的外在数据，从而允许按顺序读取外部数据。

公开(公告)号：US07496074B2

公开(公告)日：2009-02-24

申请号：US10414125

申请日：2003-04-15

申请人： Edward L. Hepler ,  Michael F. Starsinic ,  David S. Bass ,  Binish Desai ,  Alan M. Levi ,  George W. McClellan ,  Douglas R. Castor

发明人： Edward L. Hepler ,  Michael F. Starsinic ,  David S. Bass ,  Binish Desai ,  Alan M. Levi ,  George W. McClellan ,  Douglas R. Castor

IPC分类号： H04B7/216

CPC分类号： H04W88/06 ,  H04B1/0067 ,  H04B1/406 ,  H04B1/707 ,  H04B7/2618 ,  H04B2201/70707 ,  H04L1/0061 ,  H04L1/0068 ,  H04L1/0071 ,  H04L1/08 ,  H04L2001/0094 ,  H04W28/18 ,  H04W74/02 ,  H04W80/00

摘要： A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

摘要翻译： 一种在无线通信系统中使用的物理层传输复合处理系统。 提供多个互连的处理块。 块通过读数据总线，写数据总线和控制总线相互连接。 这些块包括传输信道处理块，复合信道处理块和码片速率处理块。 至少两个块能够处理多种无线格式的数据。 对于特定的无线模式，第一组参数被编程到块中。 操作块以特定的无线格式模式处理数据。

公开(公告)号：US4494193A

公开(公告)日：1985-01-15

申请号：US430396

申请日：1982-09-30

申请人： David J. Brahm ,  James M. Grinn ,  Edward L. Hepler ,  John M. Sullivan

发明人： David J. Brahm ,  James M. Grinn ,  Edward L. Hepler ,  John M. Sullivan

IPC分类号： G06F13/20 ,  G06F9/52 ,  G06F13/14 ,  G06F13/40 ,  H04L29/08 ,  G06F1/00

CPC分类号： G06F13/4036

摘要： In a communication system which includes a plurality of stations interconnected for communications by a first bus, a second station includes a device, such as a processor, and a resource, such as a memory or a peripheral unit, interconnected for communication by a second bus. An interface mechanism connecting the first bus with the second bus allows the device to access the first bus over the second bus, and allows a first station to access the resource via the first and second buses. Deadlock detection circuitry detects cotemporaneous attempts by the device to access the first bus and attempts by the first station to access the resource. Deadlock resolution circuitry responds to deadlock detection by disconnecting the device from the second bus to allow the first station to access the resource, and by reconnecting the device to the second bus when the first station ceases to access the resource. If the device is operating under program control, the deadlock detection and resolution are transparent to the program.

摘要翻译： 在包括由第一总线进行通信的互连的多个站的通信系统中，第二站包括诸如处理器的设备，以及互连以供第二总线通信的资源，诸如存储器或外围设备 。 将第一总线与第二总线连接的接口机构允许设备通过第二总线访问第一总线，并允许第一站通过第一和第二总线访问资源。 死锁检测电路检测设备访问第一总线并尝试由第一站访问资源的同时尝试。 死锁分辨率电路通过将设备与第二总线断开连接来响应死锁检测，以允许第一站访问资源，并且当第一站停止访问资源时，将设备重新连接到第二总线。 如果设备在程序控制下运行，则死锁检测和分辨率对程序是透明的。