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    FPGA having fast configuration memory data readback
    31.
    发明授权
    FPGA having fast configuration memory data readback 有权
    FPGA具有快速配置存储器数据回读

    公开(公告)号：US6069489A

    公开(公告)日：2000-05-30

    申请号：US128733

    申请日：1998-08-04

    申请人： Roman Iwanczuk ,  Steven P. Young ,  David P. Schultz

    发明人： Roman Iwanczuk ,  Steven P. Young ,  David P. Schultz

    IPC分类号： H03K19/177 ,  G06F7/38

    CPC分类号： H03K19/17776 ,  H03K19/17748 ,  H03K19/1776

    摘要： An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer. Using the invention, a bit stream designed for an old device can be used for a new device having additional configuration memory cells.

    摘要翻译： FPGA配置存储器被分成具有唯一地址的柱状帧。 配置数据被加载到配置寄存器中，并且并行传送配置数据。 在优选实施例中，输入寄存器，影子输入寄存器和多路复用器阵列允许使用比常规FPGA更大数量的输入位的有效配置数据传送。 灵活的外部接口使得能够连接到从预定最大宽度到其选定分数的总线大小。 通过使用影子寄存器以最小的延迟逐帧地将这样的数据驱动到存储器单元中，并且通过采用多路复用器阵列来利用更宽的配置数据传输总线，使配置数据传输更有效。 通过采用支持双向数据传输的配置寄存器逻辑，配置回读的速度基本上等于输入配置数据的速率。 使用本发明，为旧设备设计的比特流可以用于具有附加配置存储单元的新设备。

    Low current power-on reset circuit
    32.
    发明授权
    Low current power-on reset circuit 失效
    低电流上电复位电路

    公开(公告)号：US6005423A

    公开(公告)日：1999-12-21

    申请号：US546345

    申请日：1995-10-20

    申请人： David P. Schultz

    发明人： David P. Schultz

    IPC分类号： H03K17/22

    CPC分类号： H03K17/223

    摘要： A power-on reset circuit responds to a power decrease of very short duration by using a delay circuit having a high threshold inverter which reliably detects a voltage as high as a standard threshold voltage as a low voltage when the power supply voltage again begins to increase. A very low current source provides current for driving the power-on reset circuit only when providing a power-on reset signal and draws no current during normal circuit operation.

    摘要翻译： 上电复位电路通过使用具有高阈值逆变器的延迟电路来响应非常短的持续时间的功率降低，当电源电压再次开始增加时，可靠地检测到作为标准阈值电压的电压为低电压为低电压 。 非常低的电流源仅在提供上电复位信号时提供用于驱动上电复位电路的电流，并且在正常电路操作期间不消耗电流。

    System and method of actuating a swashplate for main rotor control
    33.
    发明授权
    System and method of actuating a swashplate for main rotor control 有权
    用于主转子控制的旋转斜盘的系统和方法

    公开(公告)号：US09156547B2

    公开(公告)日：2015-10-13

    申请号：US13370130

    申请日：2012-02-09

    申请人： Corey J. Dickman ,  Carlos A. Fenny ,  David P. Schultz

    发明人： Corey J. Dickman ,  Carlos A. Fenny ,  David P. Schultz

    IPC分类号： F01D7/00 ,  B64C27/605 ,  F15B18/00

    CPC分类号： B64C27/605 ,  F15B18/00

    摘要： The main rotor control system includes a rise/fall swashplate assembly that is coupled to three triplex actuators. The swashplate assembly is configured to provide full collective and cyclic pitch controls. Each triplex actuator includes three piston/cylinder assemblies in parallel. Selective actuation of each triplex actuator is controlled by a fly-by-wire system in conjunction with three flight control computers and three hydraulic power packs. Integrated three function valves can be associated with an individual manifold for each piston/cylinder assembly of each triplex actuator, the integrated three function valve be configured to insure safe operation of the triplex actuator during a failure of a certain piston/cylinder assembly.

    摘要翻译： 主转子控制系统包括一个上升/下降斜盘组件，它与三个三重执行器相连。 斜盘组件被配置为提供完整的集体和循环俯仰控制。 每个三重执行器都包括并联的三个活塞/气缸组件。 每个三重执行机构的选择性致动由三线式控制计算机和三台液压动力组件联合控制。 集成的三功能阀可以与每个三重执行器的每个活塞/气缸组件的单独歧管相关联，集成的三功能阀被配置为在某个活塞/气缸组件的故障期间确保三重致动器的安全操作。

    Error checking parity and syndrome of a block of data with relocated parity bits
    34.
    发明授权
    Error checking parity and syndrome of a block of data with relocated parity bits 有权
    错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验

    公开(公告)号：US08301988B1

    公开(公告)日：2012-10-30

    申请号：US13005475

    申请日：2011-01-12

    申请人： Warren E. Cory ,  David P. Schultz ,  Steven P. Young

    发明人： Warren E. Cory ,  David P. Schultz ,  Steven P. Young

    IPC分类号： H03M13/00

    CPC分类号： H03M13/27 ,  H03M13/19 ,  H03M13/45

    摘要： An apparatus for error checking is described. The apparatus includes a matrix having a plurality of bit position columns and rows, where the bit position columns are equal in number to data bits of a word length, the word length for a word serial transmission of a data vector, where the bit position columns are one each for each data bit. The bit position rows are equal in number to syndrome bits, and the bit position rows are one each for each syndrome bit. A portion of the bit position columns are allocated to parity bits for a selected word of the data vector, where the portion of the bit position columns for the selected word are one each for each parity bit allocated to the selected word.

    摘要翻译： 描述用于错误检查的装置。 该装置包括具有多个位位列和行的矩阵，其中位位列的数量与字长度的数据位相等，数据向量的字串行传输的字长，其中位位置列 每个数据位都是一个。 位位置行的数量与校正子位数相等，并且位位置行对于每个校正子位都是一个。 比特位列的一部分被分配给数据向量的所选字的奇偶校验位，其中所选字的位位列的部分对于分配给所选字的每个奇偶校验位都是一个。

    Error correction for multiple word read
    35.
    发明授权
    Error correction for multiple word read 有权
    错误纠正多个字读

    公开(公告)号：US07430703B1

    公开(公告)日：2008-09-30

    申请号：US11135979

    申请日：2005-05-24

    申请人： David P. Schultz

    发明人： David P. Schultz

    IPC分类号： G11C29/00

    CPC分类号： H03K19/1776 ,  G06F11/1008 ,  G11C2029/0411 ,  H03K19/17764

    摘要： An integrated circuit that accesses memory from data lines in multiple word increments having distributed error correction coding circuitry is described. The data lines are selectively coupled to a portion of the memory for a read of data stored in the portion of the memory. The read includes providing in parallel in the multiple word increments the data stored in the portion of the memory. The data lines are selectively tapped to provide the data from the read to flow in parallel in a first direction and in a second direction. The first direction provides the data to the data registers, and the second direction provides the data to be propagated in an error checking matrix of the distributed error correction coding circuitry.

    摘要翻译： 描述了以具有分布式纠错编码电路的多字增量从数据线访问存储器的集成电路。 数据线被选择性地耦合到存储器的一部分，用于读取存储在存储器的该部分中的数据。 读取包括以多个字并行地提供存储在存储器部分中的数据。 数据线被选择性地抽头以从第一方向和第二方向平行地提供从读取到流的数据。 第一方向将数据提供给数据寄存器，第二方向提供要在分布式纠错编码电路的错误校验矩阵中传播的数据。

    Error checking parity and syndrome of a block of data with relocated parity bits
    36.
    发明授权
    Error checking parity and syndrome of a block of data with relocated parity bits 有权
    错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验

    公开(公告)号：US07426678B1

    公开(公告)日：2008-09-16

    申请号：US10971220

    申请日：2004-10-22

    申请人： Warren E. Cory ,  David P. Schultz ,  Steven P. Young

    发明人： Warren E. Cory ,  David P. Schultz ,  Steven P. Young

    IPC分类号： H03M13/00

    CPC分类号： H03M13/27 ,  H03M13/19 ,  H03M13/45

    摘要： Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.

    摘要翻译： 描述了用于错误检查信息的方法和装置。 配置数据包括数据位和奇偶校验位。 值得注意的是，可以重新定位奇偶校验位以确定校正子值。 通过对配置数据的串行发送的每个字计算部分校正子值来确定综合征位，其中配置数据包括一个或多个数据向量。 识别配置数据的每个单词的位置。 确定部分综合征值是否是初始部分综合征值或响应于词位置的其他部分综合征值。 存储初始部分综合征值，并且随后的部分综合征值被累积地添加到数据向量的每个单词以得到数据向量的校正子值。

    Programmable gate array and embedded circuitry initialization and processing
    40.
    发明授权
    Programmable gate array and embedded circuitry initialization and processing 有权
    可编程门阵列和嵌入式电路的初始化和处理

    公开(公告)号：US07420392B2

    公开(公告)日：2008-09-02

    申请号：US10898582

    申请日：2004-07-23

    申请人： David P. Schultz ,  Stephen M. Douglass ,  Steven P. Young ,  Nigel G. Herron ,  Mehul R. Vashi ,  Jane W. Sowards

    发明人： David P. Schultz ,  Stephen M. Douglass ,  Steven P. Young ,  Nigel G. Herron ,  Mehul R. Vashi ,  Jane W. Sowards

    IPC分类号： H01L25/00 ,  H03K19/173

    CPC分类号： H03K19/17772 ,  G06F15/7867 ,  H03K17/22 ,  H03K19/0016 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/17796

    摘要： Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.

    摘要翻译： 互连逻辑提供嵌入式固定逻辑电路或电路与可编程门阵列的可编程逻辑结构的连接，使得固定逻辑电路用作可编程逻辑结构的扩展。 互连逻辑包括互连瓦片，并且还可以包括接口逻辑。 互连瓦片提供了固定逻辑电路的输入和/或输出之间的选择性连接以及可编程逻辑结构的互连。 接口逻辑（包含在内）提供逻辑电路，用于对固定逻辑电路和可编程逻辑结构之间的数据传输进行调节。 在一个操作中，可编程逻辑结构在固定逻辑电路的启动/引导顺序之前被配置。 在另一个操作中，固定逻辑电路被启动并用于配置可编程逻辑结构。