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1.发明授权Error checking parity and syndrome of a block of data with relocated parity bits 有权错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验公开(公告)号：US07895509B1
公开(公告)日：2011-02-22
申请号：US12188935
申请日：2008-08-08
摘要： Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.
摘要翻译： 描述了用于错误检查信息的方法和装置。 配置数据包括数据位和奇偶校验位。 值得注意的是，可以重新定位奇偶校验位以确定校正子值。 通过对配置数据的串行发送的每个字计算部分校正子值来确定综合征位，其中配置数据包括一个或多个数据向量。 识别配置数据的每个单词的位置。 确定部分综合征值是否是初始部分综合征值或响应于词位置的其他部分综合征值。 存储初始部分综合征值，并且随后的部分综合征值被累积地添加到数据向量的每个单词以得到数据向量的校正子值。
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2.发明授权Error checking parity and syndrome of a block of data with relocated parity bits 有权错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验公开(公告)号：US08301988B1
公开(公告)日：2012-10-30
申请号：US13005475
申请日：2011-01-12
IPC分类号： H03M13/00
摘要： An apparatus for error checking is described. The apparatus includes a matrix having a plurality of bit position columns and rows, where the bit position columns are equal in number to data bits of a word length, the word length for a word serial transmission of a data vector, where the bit position columns are one each for each data bit. The bit position rows are equal in number to syndrome bits, and the bit position rows are one each for each syndrome bit. A portion of the bit position columns are allocated to parity bits for a selected word of the data vector, where the portion of the bit position columns for the selected word are one each for each parity bit allocated to the selected word.
摘要翻译： 描述用于错误检查的装置。 该装置包括具有多个位位列和行的矩阵，其中位位列的数量与字长度的数据位相等，数据向量的字串行传输的字长，其中位位置列 每个数据位都是一个。 位位置行的数量与校正子位数相等，并且位位置行对于每个校正子位都是一个。 比特位列的一部分被分配给数据向量的所选字的奇偶校验位，其中所选字的位位列的部分对于分配给所选字的每个奇偶校验位都是一个。
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3.发明授权Error checking parity and syndrome of a block of data with relocated parity bits 有权错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验公开(公告)号：US07426678B1
公开(公告)日：2008-09-16
申请号：US10971220
申请日：2004-10-22
IPC分类号： H03M13/00
摘要： Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.
摘要翻译： 描述了用于错误检查信息的方法和装置。 配置数据包括数据位和奇偶校验位。 值得注意的是，可以重新定位奇偶校验位以确定校正子值。 通过对配置数据的串行发送的每个字计算部分校正子值来确定综合征位，其中配置数据包括一个或多个数据向量。 识别配置数据的每个单词的位置。 确定部分综合征值是否是初始部分综合征值或响应于词位置的其他部分综合征值。 存储初始部分综合征值，并且随后的部分综合征值被累积地添加到数据向量的每个单词以得到数据向量的校正子值。
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4.发明授权Error checking parity and syndrome of a block of data with relocated parity bits 有权错误检查具有重定位奇偶校验位的数据块的奇偶校验和校验公开(公告)号：US08245102B1
公开(公告)日：2012-08-14
申请号：US12188939
申请日：2008-08-08
IPC分类号： G06F11/00
摘要： Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for each word serially transmitted of the configuration data, where the configuration data includes one or more data vectors. Location of each word of the configuration data is identified. It is determined whether a partial syndrome value is an initial partial syndrome value or other partial syndrome value responsive to word location. An initial partial syndrome value is stored, and subsequent partial syndrome values are cumulatively added for each word of a data vector to arrive at a syndrome value for the data vector.
摘要翻译： 描述了用于错误检查信息的方法和装置。 配置数据包括数据位和奇偶校验位。 值得注意的是，可以重新定位奇偶校验位以确定校正子值。 通过对配置数据的串行发送的每个字计算部分校正子值来确定综合征位，其中配置数据包括一个或多个数据向量。 识别配置数据的每个单词的位置。 确定部分综合征值是否是初始部分综合征值或响应于词位置的其他部分综合征值。 存储初始部分综合征值，并且随后的部分综合征值被累积地添加到数据向量的每个单词以得到数据向量的校正子值。
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公开(公告)号：US07314174B1
公开(公告)日：2008-01-01
申请号：US10970964
申请日：2004-10-22
CPC分类号： H03K19/177
摘要： A system for programming configuration memory cells in an integrated circuit. The system includes: a set of data registers, wherein a member of the set has a temporary storage for a fixed number of configuration bits; and a plurality of rows, each row has a plurality of columns, wherein configuration memory cells in a selected column and in a selected row are programmed using the fixed number of configuration bits.
摘要翻译： 一种用于在集成电路中编程配置存储单元的系统。 该系统包括：一组数据寄存器，其中该组的成员具有固定数量的配置位的临时存储; 和多行，每行具有多个列，其中使用固定数量的配置位对所选列和所选行中的配置存储单元进行编程。
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6.发明授权Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability 有权具有增强的全故障覆盖存储器单元可测性的存储器中的分段数据线方案公开(公告)号：US07142442B1
公开(公告)日：2006-11-28
申请号：US10796750
申请日：2004-03-08
CPC分类号： G11C29/50 , G11C7/12 , G11C11/41 , G11C11/419 , G11C2029/1204
摘要： A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A control circuit is coupled to at least one row segment, and provides control signals to the at least one row segment and to the dataline driver circuits.
摘要翻译： 存储器包括多个行段，其中每个行段具有耦合到对应的数据段段对的多个存储器单元。 数据线驱动器电路提供在行段之间以缓冲相邻数据段上的信号。 控制电路耦合到至少一个行段，并且向至少一个行段和数据线驱动器电路提供控制信号。
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7.发明授权Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA 有权用于读取，修改和写入FPGA的选定配置存储单元的方法和结构公开(公告)号：US06255848B1
公开(公告)日：2001-07-03
申请号：US09374472
申请日：1999-08-13
IPC分类号： H01L2500
CPC分类号： H03K19/1776
摘要： An FPGA configuration circuit including a mask register that stores mask data during configuration memory read-modify-write operations. The mask data enables a multiplexing circuit to overwrite selected memory cells in a configuration memory array with new data bit values. Data bit values from all other memory cells in the configuration memory array are fed back by the multiplexing circuit. In one embodiment, the new data bit values are transmitted on a bi-directional bus and stored in a shift register. The configuration memory array is arranged in frames that are addressed by a frame address register, and the contents of an addressed frame are written to a shadow register. Under the control of the mask register, the multiplexing circuit modifies the frame data bit values stored in the shadow register using the new data bit values stored in the shift register. The contents of the shadow register are then written into the addressed frame.
摘要翻译： FPGA配置电路，包括在配置存储器读 - 修改 - 写操作期间存储掩模数据的掩码寄存器。 掩模数据使多路复用电路可以用新的数据位值覆盖配置存储器阵列中的选定存储单元。 配置存储器阵列中所有其他存储单元的数据位值由复用电路反馈。 在一个实施例中，新的数据位值在双向总线上传输并存储在移位寄存器中。 配置存储器阵列被布置成由帧地址寄存器寻址的帧，并且寻址帧的内容被写入影子寄存器。 在掩码寄存器的控制下，复用电路使用存储在移位寄存器中的新数据位值来修改存储在影子寄存器中的帧数据位值。 然后将影子寄存器的内容写入寻址帧。
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公开(公告)号：US6097210A
公开(公告)日：2000-08-01
申请号：US128965
申请日：1998-08-04
IPC分类号： H03K19/177 , G01N33/00
CPC分类号： H03K19/17776 , H03K19/17736 , H03K19/17748 , H03K19/1776 , H03K19/1778
摘要： An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer. Using the invention, a bit stream designed for an old device can be used for a new device having additional configuration memory cells.
摘要翻译： FPGA配置存储器被分成具有唯一地址的柱状帧。 配置数据被加载到配置寄存器中，并且并行传送配置数据。 在优选实施例中，输入寄存器，影子输入寄存器和多路复用器阵列允许使用比常规FPGA更大数量的输入位的有效配置数据传送。 灵活的外部接口使得能够连接到从预定最大宽度到其选定分数的总线大小。 通过使用影子寄存器以最小的延迟逐帧地将这样的数据驱动到存储器单元中，并且通过采用多路复用器阵列来利用更宽的配置数据传输总线，使配置数据传输更有效。 通过采用支持双向数据传输的配置寄存器逻辑，配置回读的速度基本上等于输入配置数据的速率。 使用本发明，为旧设备设计的比特流可以用于具有附加配置存储单元的新设备。
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公开(公告)号：US6069489A
公开(公告)日：2000-05-30
申请号：US128733
申请日：1998-08-04
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/17776 , H03K19/17748 , H03K19/1776
摘要： An FPGA configuration memory is divided into columnar frames each having a unique address. Configuration data is loaded into a configuration register, which transfers configuration data frame by frame in parallel. In a preferred embodiment, an input register, a shadow input register and a multiplexer array permit efficient configuration data transfer using a larger number of input bits than conventional FPGAs. A flexible external interface enables connection with bus sizes varying from a predetermined maximum width down to a selected fraction thereof. Configuration data transfer is made more efficient by using shadow registers to drive such data into memory cells on a frame-by-frame basis with a minimum of delay, and by employing a multiplexer array to exploit a wider configuration data transfer bus. The speed of configuration readback is made substantially equal to the rate of configuration data input by employing configuration register logic that supports bidirectional data transfer. Using the invention, a bit stream designed for an old device can be used for a new device having additional configuration memory cells.
摘要翻译： FPGA配置存储器被分成具有唯一地址的柱状帧。 配置数据被加载到配置寄存器中，并且并行传送配置数据。 在优选实施例中，输入寄存器，影子输入寄存器和多路复用器阵列允许使用比常规FPGA更大数量的输入位的有效配置数据传送。 灵活的外部接口使得能够连接到从预定最大宽度到其选定分数的总线大小。 通过使用影子寄存器以最小的延迟逐帧地将这样的数据驱动到存储器单元中，并且通过采用多路复用器阵列来利用更宽的配置数据传输总线，使配置数据传输更有效。 通过采用支持双向数据传输的配置寄存器逻辑，配置回读的速度基本上等于输入配置数据的速率。 使用本发明，为旧设备设计的比特流可以用于具有附加配置存储单元的新设备。
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10.发明授权公开(公告)号：US07420392B2
公开(公告)日：2008-09-02
申请号：US10898582
申请日：2004-07-23
申请人： David P. Schultz , Stephen M. Douglass , Steven P. Young , Nigel G. Herron , Mehul R. Vashi , Jane W. Sowards
发明人： David P. Schultz , Stephen M. Douglass , Steven P. Young , Nigel G. Herron , Mehul R. Vashi , Jane W. Sowards
IPC分类号： H01L25/00 , H03K19/173
CPC分类号： H03K19/17772 , G06F15/7867 , H03K17/22 , H03K19/0016 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interfacing logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and interconnect of the programmable logic fabric. The interfacing logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. In one operation, the programmable logic fabric is configured prior to the startup/boot sequence of the fixed logic circuit. In another operation, the fixed logic circuit is started up and is employed to configure the programmable logic fabric.
摘要翻译： 互连逻辑提供嵌入式固定逻辑电路或电路与可编程门阵列的可编程逻辑结构的连接，使得固定逻辑电路用作可编程逻辑结构的扩展。 互连逻辑包括互连瓦片，并且还可以包括接口逻辑。 互连瓦片提供了固定逻辑电路的输入和/或输出之间的选择性连接以及可编程逻辑结构的互连。 接口逻辑（包含在内）提供逻辑电路，用于对固定逻辑电路和可编程逻辑结构之间的数据传输进行调节。 在一个操作中，可编程逻辑结构在固定逻辑电路的启动/引导顺序之前被配置。 在另一个操作中，固定逻辑电路被启动并用于配置可编程逻辑结构。
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