公开(公告)号：US11069772B2

公开(公告)日：2021-07-20

申请号：US16221034

申请日：2018-12-14

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423

Abstract: Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.

公开(公告)号：US11063115B2

公开(公告)日：2021-07-13

申请号：US16708001

申请日：2019-12-09

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Yang Sui

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/08 ,  H01L21/761 ,  H01L29/10 ,  H01L29/739 ,  H01L29/872

Abstract: Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.

公开(公告)号：US20200258985A1

公开(公告)日：2020-08-13

申请号：US16789164

申请日：2020-02-12

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/16 ,  H01L29/78 ,  H01L21/04 ,  H01L29/745 ,  H01L29/739 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US20200185493A1

公开(公告)日：2020-06-11

申请号：US16708001

申请日：2019-12-09

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Yang Sui

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L21/761 ,  H01L29/16 ,  H01L29/78 ,  H01L29/08

Abstract: Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.

公开(公告)号：US10600871B2

公开(公告)日：2020-03-24

申请号：US15595643

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/04 ,  H01L29/10 ,  H01L29/739 ,  H01L29/745 ,  H01L29/74

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US10388737B2

公开(公告)日：2019-08-20

申请号：US15601754

申请日：2017-05-22

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/745 ,  H01L29/74

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices. In particular, the present disclosure relates to shielding regions for use in combination with an optimization layer. The disclosed shielding regions reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a portion of the JFET region between adjacent device cells and interrupt the continuity of the optimization layer in a widest portion of the JFET region, where the corners of neighboring device cells meet. The disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US10347489B2

公开(公告)日：2019-07-09

申请号：US13933366

申请日：2013-07-02

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Stacey Joy Kennerly

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/74

Abstract: A method of manufacturing a semiconductor device is presented. The method includes providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with a first dopant type. The method further includes implanting the semiconductor layer with a second dopant type using a single implantation mask and a substantially similar implantation dose to form a second region and a junction termination extension (JTE) in the semiconductor layer, wherein the implantation dose is in a range from about 2×1013 cm−2 to about 12×1013 cm−2. Semiconductor devices are also presented.

公开(公告)号：US20190088479A1

公开(公告)日：2019-03-21

申请号：US15953037

申请日：2018-04-13

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Reza Ghandi ,  David Alan Lilienfeld

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/36 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.

公开(公告)号：US10211304B2

公开(公告)日：2019-02-19

申请号：US14097075

申请日：2013-12-04

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/417 ,  H01L23/544 ,  H01L29/04 ,  H01L29/06

Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.). A semiconductor device includes a well region extending a first depth into a surface of an epitaxial semiconductor layer positioned above a drift region. The device includes a junction field-effect transistor (JFET) region positioned adjacent to the well region in the epitaxial semiconductor layer. The device also includes a trench extending a second depth into the JFET region, wherein the trench comprises a bottom and a sidewall that extends down to the bottom at an angle relative to the surface of the epitaxial semiconductor layer.

公开(公告)号：US10199465B2

公开(公告)日：2019-02-05

申请号：US14313820

申请日：2014-06-24

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/76 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/739 ,  H01L29/06

Abstract: A method of fabricating a semiconductor device cell at a surface of a silicon carbide (SiC) semiconductor layer includes forming a segmented source and body contact (SSBC) of the semiconductor device cell over the surface of the SiC semiconductor layer. The SSBC includes a body contact portion disposed over the surface of the semiconductor layer and proximate to a body contact region of the semiconductor device cell, wherein the body contact portion is not disposed over the center of the semiconductor device cell. The SSBC also includes a source contact portion disposed over the surface of the semiconductor layer and proximate to a source contact region of the semiconductor device cell, wherein the at least one source contact portion only partially surrounds the body contact portion of the SSBC.