公开(公告)号：US06557048B1

公开(公告)日：2003-04-29

申请号：US09431364

申请日：1999-11-01

申请人： James B. Keller ,  Derrick R. Meyer ,  Dale E. Gulick ,  Larry D. Hewitt

发明人： James B. Keller ,  Derrick R. Meyer ,  Dale E. Gulick ,  Larry D. Hewitt

IPC分类号： G06F1300

CPC分类号： G06F13/4059

摘要： A computer system is presented which implements a system and method for ordering input/output (I/O) memory operations. In one embodiment, the computer system includes a processing subsystem and an I/O subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor executing software instructions. The I/O subsystem includes one or more I/O nodes serially coupled via non-coherent communication links. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). One of the processing nodes includes a host bridge which translates packets moving between the processing subsystem and the I/O subsystem. One of the I/O nodes is coupled to the processing node including the host bridges. The I/O node coupled to the processing node produces and/or provides transactions having destinations or targets within the processing subsystem to the processing node including the host bridge. The I/O node may, for example, produce and/or provide a first transaction followed by a second transaction. The host bridge may dispatch the second transaction with respect to the first transaction according to a predetermined set of ordering rules. For example, the host bridge may: (i) receive the first and second transactions, (ii) dispatch the first transaction within the processing subsystem, and (iii) dispatch the second transaction within the processing subsystem dependent upon progress of the first transaction within the processing subsystem and the predetermined set of ordering rules.

摘要翻译： 提出了一种实现用于排序输入/输出（I / O）存储器操作的系统和方法的计算机系统。 在一个实施例中，计算机系统包括处理子系统和I / O子系统。 处理子系统包括通过相干通信链路互连的多个处理节点。 每个处理节点可以包括执行软件指令的处理器。 I / O子系统包括通过非相干通信链路串联耦合的一个或多个I / O节点。 每个I / O节点可以体现一个或多个I / O功能（例如，调制解调器，声卡等）。 其中一个处理节点包括一个主机桥，它转换在处理子系统和I / O子系统之间移动的数据包。 其中一个I / O节点耦合到包括主机桥的处理节点。 耦合到处理节点的I / O节点产生和/或提供具有处理子系统内包含主机桥的处理节点的目的地或目标的事务。 I / O节点可以例如产生和/或提供第一事务，随后是第二事务。 主桥可以根据预定的一组排序规则来分派关于第一事务的第二事务。 例如，主桥可以：（i）接收第一和第二事务，（ii）在处理子系统内调度第一事务，以及（iii）根据第一事务的进度在处理子系统内调度第二事务 处理子系统和预定的一套排序规则。

公开(公告)号：US06457084B1

公开(公告)日：2002-09-24

申请号：US09330528

申请日：1999-06-11

申请人： Dale E. Gulick ,  Geoffrey S. S. Strongin

发明人： Dale E. Gulick ,  Geoffrey S. S. Strongin

IPC分类号： G06F1314

CPC分类号： G06F13/36

摘要： A computer system includes a first integrated circuit having a first function and a second integrated circuit having a plurality of second functions. A communication link connects the first integrated circuit and the second integrated circuit. The communication link includes at least one logical pipe having a source side on the first circuit and a target side on the second integrated circuit, the one pipe carrying transactions over the communication link between the first function and the second functions. The pipe is identified by a pipe identification carried in the transactions. A target side distributor circuit is coupled between the second functions and the communication link. The target side distributor circuit receives those transactions from the communication link having the pipe identification. The target side distributor circuit provides transactions received from the communication link having the pipe identification to respective ones of the second functions according to an address field included in the transactions.

摘要翻译： 计算机系统包括具有第一功能的第一集成电路和具有多个第二功能的第二集成电路。 通信链路连接第一集成电路和第二集成电路。 通信链路包括至少一个在第一电路上具有源侧和第二集成电路上的目标侧的逻辑管，所述一个管道通过第一功能和第二功能之间的通信链路进行交易。 管道由交易中携带的管道标识识别。 目标侧分配器电路耦合在第二功能和通信链路之间。 目标侧分配器电路从具有管道识别的通信链路接收那些事务。 目标侧分配器电路根据包括在事务中的地址字段，将具有管道标识的通信链路接收的交易提供给相应的第二功能。

公开(公告)号：US06457081B1

公开(公告)日：2002-09-24

申请号：US09330636

申请日：1999-06-11

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F1314

CPC分类号： G06F13/4265

摘要： A read request is sent from a source to a target over a requesting all available data. The requester does not know the amount of data available. The response to the read request includes the available requested data along with an indication of how much available requested data is being returned.

摘要翻译： 读请求通过请求所有可用数据从源发送到目标。 请求者不知道可用数据量。 对读取请求的响应包括可用的请求数据以及返回多少可用请求数据的指示。

公开(公告)号：US06202164B1

公开(公告)日：2001-03-13

申请号：US09109822

申请日：1998-07-02

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F1300

CPC分类号： H04L12/40058 ,  G06F1/08 ,  G06F5/06 ,  G06F13/423 ,  G06F2205/061 ,  H04L12/40123 ,  H04N5/232

摘要： A master isochronous clock structure wherein a frame-rate clock of a plurality of data buses are synchronized to a master clock signal. The master clock signal may be derived from the existing clocks signals within the computer system or from data received from an external source. The master clock signal may also be used by an operating system scheduler to schedule task that generate or consume blocks of isochronous data. In an alternative embodiment, the drift of a device clock signal relative to a master clock signal is measured and used to synchronize the device clock signal. For example, a mechanism may monitor the level of data in a data buffer. The level of data in the data buffer is a measure of the drift between the clock generating the data and the clock consuming the data. Based upon the level of data in the buffer, synchronization information is provided to synchronize the rates of the clock signals that generate and consume the data. In one embodiment, the level of data in a data buffer is used to synchronize the clock of a video camera. In another embodiment, the level of data in a data buffer is used to synchronize a clock of a telephony codec.

摘要翻译： 一种主同步时钟结构，其中多个数据总线的帧速率时钟与主时钟信号同步。 主时钟信号可以从计算机系统内的现有时钟信号或从外部源接收的数据中导出。 主时钟信号也可由操作系统调度器用于调度生成或消耗同步数据块的任务。 在替代实施例中，测量器件时钟信号相对于主时钟信号的漂移并用于同步器件时钟信号。 例如，机制可以监视数据缓冲器中的数据级别。 数据缓冲器中的数据电平是产生数据的时钟与消耗数据的时钟之间的漂移的量度。 基于缓冲器中的数据级别，提供同步信息以同步产生和消耗数据的时钟信号的速率。 在一个实施例中，使用数据缓冲器中的数据级别来同步摄像机的时钟。 在另一个实施例中，数据缓冲器中的数据级别用于同步电话编解码器的时钟。

公开(公告)号：US06195749B1

公开(公告)日：2001-02-27

申请号：US09501888

申请日：2000-02-10

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F9445

CPC分类号： G06F9/4401

摘要： A computer system including a memory access controller for using non-system memory storage resources during system boot time. A computer system includes a microprocessor, a system memory and a plurality of peripheral devices coupled to the microprocessor through one or more buses. A system controller and a peripheral bus controller control the buses. Many peripheral device controllers contain buffer memory used during normal system operation, by the peripheral device controllers, to buffer data between the computer system and the peripheral devices. The computer system also includes a memory access controller and a configuration storage unit. The configuration storage unit stores configuration control information which causes control logic to configure the buffer memory. The memory access controller controls accesses to the buffer memory associated with the peripheral devices during system initialization to allow use of the buffer memory as a stack or scratchpad RAM.

摘要翻译： 一种包括用于在系统启动时使用非系统存储器存储资源的存储器访问控制器的计算机系统。 计算机系统包括微处理器，系统存储器和通过一个或多个总线耦合到微处理器的多个外围设备。 系统控制器和外围总线控制器控制总线。 许多外围设备控制器包含在正常系统操作期间由外围设备控制器在计算机系统和外围设备之间缓冲数据所使用的缓冲存储器。 计算机系统还包括存储器访问控制器和配置存储单元。 配置存储单元存储使控制逻辑配置缓冲存储器的配置控制信息。 存储器访问控制器在系统初始化期间控制与外围设备相关联的缓冲存储器的访问，以允许将缓冲存储器用作堆栈或暂存器RAM。

公开(公告)号：US6167492A

公开(公告)日：2000-12-26

申请号：US220487

申请日：1998-12-23

申请人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

发明人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

IPC分类号： G06F13/16 ,  G06F13/00 ,  G06F12/00

CPC分类号： G06F13/1621

摘要： A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access transactions further include first and second pipe identifications, respectively. The node circuit maps the first and second memory addresses to first and second node numbers, respectively. The first and second pipe identifications are compared. If the first and second pipe identifications compare equally, then the first and second node numbers are compared. First and second coherent memory access transactions are generated by the node coupled to the I/O bridge wherein the first and second coherent memory access transactions correspond to the first and second non-coherent memory access transactions, respectively. The first coherent memory access transaction is transmitted to one of the nodes of the multiprocessor computer system. However, the second coherent memory access transaction is not transmitted unless the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

公开(公告)号：US6101560A

公开(公告)日：2000-08-08

申请号：US866652

申请日：1997-05-30

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F13/38 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4027 ,  G06F13/385 ,  G06F13/405 ,  Y02B60/1228 ,  Y02B60/1235

摘要： An apparatus includes a game port interface and a bus. The game port interface includes first and second game port portions. The first game port portion is on a first integrated circuit and interfaces to an I/O bus. The second game port portion is on a second integrated circuit and provides I/O terminals to couple the game port interface to a peripheral device. The bus couples the first and second integrated circuits. The bus is for serially transferring game port information between the first and second game port portions.

摘要翻译： 一种装置包括游戏端口接口和总线。 游戏端口接口包括第一和第二游戏端口部分。 第一游戏端口部分在第一集成电路上并且与I / O总线接口。 第二游戏端口部分在第二集成电路上并且提供I / O终端以将游戏端口接口耦合到外围设备。 总线耦合第一和第二集成电路。 总线用于在第一和第二游戏端口部分之间串行传送游戏端口信息。

公开(公告)号：US6085270A

公开(公告)日：2000-07-04

申请号：US98655

申请日：1998-06-17

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F13/42 ,  G06F13/00 ,  H04L12/50

CPC分类号： G06F13/4243

摘要： An isochronous bus may includes a data signal, a data valid signal, a frame synch signal and a clock signal. The bandwidth of the data signal is partitioned into a plurality of frames. The frame rate may be selected based upon the sample rate of one of the isochronous devices connected to the isochronous bus or maybe some divisor of the data rate of the isochronous bus. Each frame is partitioned into a plurality of data channels. Each data channel transmits data from an isochronous device. A number of bit time slots are allocated to each data channel. The number of bit time slots allocated to each data channel varies based upon the sample rate of the device corresponding to the data channel. In one embodiment, each data channel is allocated more bit time slots than the nominal samples of its corresponding device. In this manner, any drift of the sample clock may be accommodated. A data valid signal is transmitted synchronous to the data signal and the clock signal. The data valid signal indicates which bit time slots include valid data. As discussed above, a data channel may be allocated more bit time slots than the expected number of samples during a frame. The drift of the sample clock of a device relative to the isochronous bus clock may be detected by monitoring the period of the data valid signal. The system may handle multiple isochronous data streams with different, non-related sample rates.

摘要翻译： 等时总线可以包括数据信号，数据有效信号，帧同步信号和时钟信号。 数据信号的带宽被划分成多个帧。 可以基于连接到等时总线的同步设备之一的采样率或者同步总线的数据速率的一些除数来选择帧速率。 每个帧被划分成多个数据信道。 每个数据通道从同步设备发送数据。 多个位时隙被分配给每个数据信道。 分配给每个数据信道的比特时隙的数量根据与数据信道相对应的设备的采样率而变化。 在一个实施例中，每个数据信道被分配比其相应设备的标称采样更多的位时隙。 以这种方式，可以适应采样时钟的任何漂移。 数据有效信号与数据信号和时钟信号同步传输。 数据有效信号指示哪些位时隙包括有效数据。 如上所述，可以在帧期间向数据信道分配比期望的样本数更多的位时隙。 可以通过监视数据有效信号的周期来检测设备相对于同步总线时钟的采样时钟的漂移。 系统可以处理具有不同的非相关采样率的多个等时数据流。

公开(公告)号：US5987560A

公开(公告)日：1999-11-16

申请号：US928034

申请日：1997-09-11

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F13/38 ,  G06F13/40 ,  G06F13/32

CPC分类号： G06F13/4027 ,  G06F13/385 ,  G06F13/405 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A flexible general input/output function utilizes a programmable logic circuit in conjunction with general purpose input/output pins. A programmable logic circuit receives the input signals from the input terminals. The programmable logic circuit program conditions the input signals and provides conditioned input signals to the remainder of the integrated circuit. An input register receives the conditioned input signals from the programmable logic circuit, and stores values representing the state of respective conditioned input signals. A transition detection circuit detects a specified transition for each of the conditioned input signals it receives and provides an indication of the specified transition. An interrupt circuit is responsive to transition indications provided from the transition detection circuit to generate an interrupt signal associated with the specified transition of a respective conditioned input signal. The integrated circuit also includes output terminals, which are coupled to the programmable logic circuit. An output register, which can be written by the system processor, provides output signals which are conditioned by the programmable logic circuit and provided to the output terminals.

摘要翻译： 灵活的一般输入/输出功能使用可编程逻辑电路和通用输入/输出引脚。 可编程逻辑电路从输入端接收输入信号。 可编程逻辑电路程序调节输入信号，并向集成电路的其余部分提供经调节的输入信号。 输入寄存器接收来自可编程逻辑电路的经调节的输入信号，并存储表示各调节输入信号的状态的值。 转换检测电路检测其接收的每个经调节的输入信号的指定转换并提供指定转换的指示。 中断电路响应于从转换检测电路提供的转换指示，以产生与各个经调节的输入信号的指定转换相关联的中断信号。 集成电路还包括耦合到可编程逻辑电路的输出端子。 可由系统处理器写入的输出寄存器提供由可编程逻辑电路调节并提供给输出端的输出信号。

公开(公告)号：US5926629A

公开(公告)日：1999-07-20

申请号：US802323

申请日：1997-02-18

申请人： Dale E. Gulick

发明人： Dale E. Gulick

IPC分类号： G06F13/42 ,  G06F13/14

CPC分类号： G06F13/423

摘要： A bus connects a first and second integrated circuit. The bus includes a frame sync line which indicates the beginning of a frame when asserted, each frame containing a predetermined number time slots. A data out line provides data from the first to the second integrated circuit. The data represents the state of signals to be provided on output terminals of the second integrated circuit. Each of the data bits is assigned one of the time slots in the frame. A data in line provides a predetermined number of second data bits from the second to the first integrated circuit during each frame. Each of the second data bits is assigned one of the time slots and includes data including data bits indicating the state of input terminals of the second integrated circuit. A clock signal defines the time slots within the frame. The bus operates to provide frames substantially continuously between the first and second integrated circuit while the first and second integrated circuits.

摘要翻译： 总线连接第一和第二集成电路。 总线包括帧同步线，其指示当被断言时帧的开始，每帧包含预定数量的时隙。 数据输出线提供从第一至第二集成电路的数据。 该数据表示在第二集成电路的输出端子上提供的信号的状态。 每个数据位被分配在帧中的一个时隙。 一行数据在每帧期间提供从第二集成电路到第一集成电路的预定数量的第二数据位。 每个第二数据位分配一个时隙，并且包括包括表示第二集成电路的输入端的状态的数据位的数据。 时钟信号定义帧内的时隙。 总线操作以在第一和第二集成电路之间在第一和第二集成电路之间基本连续地提供帧。