公开(公告)号：US06557048B1

公开(公告)日：2003-04-29

申请号：US09431364

申请日：1999-11-01

申请人： James B. Keller ,  Derrick R. Meyer ,  Dale E. Gulick ,  Larry D. Hewitt

发明人： James B. Keller ,  Derrick R. Meyer ,  Dale E. Gulick ,  Larry D. Hewitt

IPC分类号： G06F1300

CPC分类号： G06F13/4059

摘要： A computer system is presented which implements a system and method for ordering input/output (I/O) memory operations. In one embodiment, the computer system includes a processing subsystem and an I/O subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor executing software instructions. The I/O subsystem includes one or more I/O nodes serially coupled via non-coherent communication links. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). One of the processing nodes includes a host bridge which translates packets moving between the processing subsystem and the I/O subsystem. One of the I/O nodes is coupled to the processing node including the host bridges. The I/O node coupled to the processing node produces and/or provides transactions having destinations or targets within the processing subsystem to the processing node including the host bridge. The I/O node may, for example, produce and/or provide a first transaction followed by a second transaction. The host bridge may dispatch the second transaction with respect to the first transaction according to a predetermined set of ordering rules. For example, the host bridge may: (i) receive the first and second transactions, (ii) dispatch the first transaction within the processing subsystem, and (iii) dispatch the second transaction within the processing subsystem dependent upon progress of the first transaction within the processing subsystem and the predetermined set of ordering rules.

摘要翻译： 提出了一种实现用于排序输入/输出（I / O）存储器操作的系统和方法的计算机系统。 在一个实施例中，计算机系统包括处理子系统和I / O子系统。 处理子系统包括通过相干通信链路互连的多个处理节点。 每个处理节点可以包括执行软件指令的处理器。 I / O子系统包括通过非相干通信链路串联耦合的一个或多个I / O节点。 每个I / O节点可以体现一个或多个I / O功能（例如，调制解调器，声卡等）。 其中一个处理节点包括一个主机桥，它转换在处理子系统和I / O子系统之间移动的数据包。 其中一个I / O节点耦合到包括主机桥的处理节点。 耦合到处理节点的I / O节点产生和/或提供具有处理子系统内包含主机桥的处理节点的目的地或目标的事务。 I / O节点可以例如产生和/或提供第一事务，随后是第二事务。 主桥可以根据预定的一组排序规则来分派关于第一事务的第二事务。 例如，主桥可以：（i）接收第一和第二事务，（ii）在处理子系统内调度第一事务，以及（iii）根据第一事务的进度在处理子系统内调度第二事务 处理子系统和预定的一套排序规则。

公开(公告)号：US07174467B1

公开(公告)日：2007-02-06

申请号：US10185171

申请日：2002-06-28

申请人： Frank P. Helms ,  Dale E. Gulick ,  Larry D. Hewitt ,  William A. Hughes ,  Paul C. Miranda ,  Derrick R. Meyer ,  Scott E. Swanstrom ,  Scott A. White

发明人： Frank P. Helms ,  Dale E. Gulick ,  Larry D. Hewitt ,  William A. Hughes ,  Paul C. Miranda ,  Derrick R. Meyer ,  Scott E. Swanstrom ,  Scott A. White

IPC分类号： G06F1/26 ,  G06F1/28 ,  G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/30083 ,  Y02D10/126 ,  Y02D10/172

摘要： A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.

摘要翻译： 利用基于消息的电源管理方法为多处理器系统提供电源管理。 在多处理器系统的一个处理器上通过输入/输出通信链路接收功率管理消息，该输入/输出通信链路为多处理器系统的处理器提供输入/输出接入。 电源管理消息包括对多处理器系统的处理器编码电源管理状态的电源管理字段。 通过输入/输出通信链路接收电力管理消息的处理器通过编码电源管理状态的一个或多个处理器间通信链路向多处理器系统中的其他处理器发送电源管理消息。

公开(公告)号：US07051218B1

公开(公告)日：2006-05-23

申请号：US10185195

申请日：2002-06-28

申请人： Dale E. Gulick ,  Frank P. Helms ,  Larry D. Hewitt ,  William A. Hughes ,  Paul C. Miranda ,  Derrick R. Meyer ,  Scott E. Swanstrom ,  Scott A. White

发明人： Dale E. Gulick ,  Frank P. Helms ,  Larry D. Hewitt ,  William A. Hughes ,  Paul C. Miranda ,  Derrick R. Meyer ,  Scott E. Swanstrom ,  Scott A. White

IPC分类号： G06F1/30 ,  G06F3/00 ,  G06F13/36

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3296 ,  G06F9/30083 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/172

摘要： A message based power management system converts legacy signals used in power management, and other signals used to differentiate between power states, to messages sent over a communication link. A system message sent on a communication link includes a field encoding the level of power management for the device receiving the system message. Further, one or more additional signals, separate from the communication link, may be used to indicate when to take action after the power management message has been received.

摘要翻译： 基于消息的电力管理系统将用于电力管理的传统信号和用于区分电力状态的其他信号转换成通过通信链路发送的消息。 在通信链路上发送的系统消息包括对接收系统消息的设备的电源管理级进行编码的字段。 此外，与通信链路分离的一个或多个附加信号可以用于指示何时在接收到电力管理消息之后采取行动。

公开(公告)号：US07146510B1

公开(公告)日：2006-12-05

申请号：US10198637

申请日：2002-07-18

申请人： Frank P. Helms ,  Derrick R. Meyer ,  Larry D. Hewitt ,  Dale E. Gulick ,  William A. Hughes ,  Scott E. Swanstrom

发明人： Frank P. Helms ,  Derrick R. Meyer ,  Larry D. Hewitt ,  Dale E. Gulick ,  William A. Hughes ,  Scott E. Swanstrom

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3296 ,  G06F9/30083 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/172

摘要： An integrated circuit is coupled to a communication link and to a separate signal line and includes programmable registers specifying communication link width and frequency. The integrated circuit responds to a change in the value of the signal line by changing the width and/or frequency of at least a portion of the communication link to the programmed value in response to a change in a logical value of the signal line, without the integrated circuit entering a reset state. The width and/or frequency may be changed during a POST routine or during system operation as part of a power management or other system function while maintaining its operational state.

摘要翻译： 集成电路耦合到通信链路和单独的信号线，并且包括指定通信链路宽度和频率的可编程寄存器。 通过将通信链路的至少一部分的宽度和/或频率响应于信号线的逻辑值的改变而改变为编程值，集成电路响应于信号线的值的变化，而没有 集成电路进入复位状态。 宽度和/或频率可以在POST程序期间或在系统操作期间作为功率管理或其他系统功能的一部分而改变，同时保持其操作状态。

公开(公告)号：US6167492A

公开(公告)日：2000-12-26

申请号：US220487

申请日：1998-12-23

申请人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

发明人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

IPC分类号： G06F13/16 ,  G06F13/00 ,  G06F12/00

CPC分类号： G06F13/1621

摘要： A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access transactions further include first and second pipe identifications, respectively. The node circuit maps the first and second memory addresses to first and second node numbers, respectively. The first and second pipe identifications are compared. If the first and second pipe identifications compare equally, then the first and second node numbers are compared. First and second coherent memory access transactions are generated by the node coupled to the I/O bridge wherein the first and second coherent memory access transactions correspond to the first and second non-coherent memory access transactions, respectively. The first coherent memory access transaction is transmitted to one of the nodes of the multiprocessor computer system. However, the second coherent memory access transaction is not transmitted unless the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

公开(公告)号：US06385705B1

公开(公告)日：2002-05-07

申请号：US09702147

申请日：2000-10-30

申请人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

发明人： James B. Keller ,  Dale E. Gulick ,  Larry D. Hewitt ,  Geoffrey Strongin

IPC分类号： G06F1300

CPC分类号： G06F13/1621

摘要： A circuit and method is disclosed for preserving the order for memory requests originating from I/O devices coupled to a multiprocessor computer system. The multiprocessor computer system includes a plurality of circuit nodes and a plurality of memories. Each circuit node includes at least one microprocessor coupled to a memory controller which in turn is coupled to one of the plurality of memories. The circuit nodes are in data communication with each other, each circuit node being uniquely identified by a node number. At least one of the circuit nodes is coupled to an I/O bridge which in turn is coupled directly or indirectly to one or more I/O devices. The I/O bridge generates non-coherent memory access transactions in response to memory access requests originating with one of the I/O devices. The circuit node coupled to the I/O bridge, receives the non-coherent memory access transactions. For example, the circuit node coupled to the I/O bridge receives first and second non-coherent memory access transactions. The first and second non-coherent memory access transactions include first and second memory addresses, respectively. The first and second non-coherent memory access transactions further include first and second pipe identifications, respectively. The node circuit maps the first and second memory addresses to first and second node numbers, respectively. The first and second pipe identifications are compared. If the first and second pipe identifications compare equally, then the first and second node numbers are compared. First and second coherent memory access transactions are generated by the node coupled to the I/O bridge wherein the first and second coherent memory access transactions correspond to the first and second non-coherent memory access transactions, respectively. The first coherent memory access transaction is transmitted to one of the nodes of the multiprocessor computer system. However, the second coherent memory access transaction is not transmitted unless the first and second pipe identifications do not compare equally or if the first and second node numbers compare equally.

公开(公告)号：US06791554B1

公开(公告)日：2004-09-14

申请号：US10034560

申请日：2001-12-27

申请人： James Mergard ,  Dale E. Gulick ,  Larry D. Hewitt

发明人： James Mergard ,  Dale E. Gulick ,  Larry D. Hewitt

IPC分类号： G06F1576

CPC分类号： G06T1/20

摘要： An I/O node for a computer system including an integrated graphics engine. An input/output node is implemented upon an integrated circuit chip. The I/O node includes a first transceiver unit, a second transceiver unit, a packet tunnel, a graphics engine and a graphics interface. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus and the second transceiver unit may receive and transmit packet transactions on a second link. The packet tunnel may convey selected packet transactions between the first and the second transceiver unit. The graphics engine may receive graphics packet transactions from the first transceiver unit and may render digital image information in response to receiving the graphics transactions. The graphics interface may receive additional graphics packet transactions from the first transceiver unit and may translate the additional graphics packet transactions into transactions suitable for transmission upon a graphics bus.

摘要翻译： 用于包括集成图形引擎的计算机系统的I / O节点。 输入/输出节点在集成电路芯片上实现。 I / O节点包括第一收发器单元，第二收发器单元，分组隧道，图形引擎和图形接口。 第一收发器单元可以在分组总线的第一链路上接收和发送分组交易，并且第二收发器单元可以在第二链路上接收和发送分组交易。 分组隧道可以在第一和第二收发器单元之间传送所选择的分组事务。 图形引擎可以从第一收发器单元接收图形分组交易，并且可以响应于接收到图形交易而呈现数字图像信息。 图形接口可以从第一收发器单元接收额外的图形分组事务，并且可以将附加的图形分组事务转换成适于在图形总线上传输的事务。

公开(公告)号：US06618782B1

公开(公告)日：2003-09-09

申请号：US09326304

申请日：1999-06-04

申请人： Dale E. Gulick ,  Larry D. Hewitt ,  Alfred Hartmann ,  Geoffrey S. S. Strongin

发明人： Dale E. Gulick ,  Larry D. Hewitt ,  Alfred Hartmann ,  Geoffrey S. S. Strongin

IPC分类号： G06F1314

CPC分类号： G06F13/36

摘要： A computer system that includes a first integrated circuit that has a plurality of first functions. The first integrated circuit is coupled to a second integrated circuit having a plurality of second functions via a communication link that includes a plurality of pipes carrying transactions on the link. Each pipe has a source end in one of the first and second integrated circuits and a target end in the other of the first and second integrated circuits. Each of the pipes is identified by a pipe identifier that uniquely identifies both the source end and the target end of a respective pipe. Each transaction on the link includes a pipe identification field containing the pipe identifier to associate each of the transactions with one of the pipes. The pipes share the link on a packet multiplexed basis. Each pipe can carry either isochronous or asynchronous transactions.

摘要翻译： 一种包括具有多个第一功能的第一集成电路的计算机系统。 第一集成电路经由通信链路耦合到具有多个第二功能的第二集成电路，该通信链路包括在链路上承载交易的多个管道。 每个管道在第一和第二集成电路之一中具有源极端，并且在第一和第二集成电路中的另一个中具有目标端。 每个管道由一个管道标识符来标识，该标识符唯一地标识了相应管道的源端和目标端。 链接上的每个事务都包括管道标识字段，其中包含管道标识符，以将每个事务与其中一个管道相关联。 管道以分组复用为基础共享链路。 每个管道可以携带同步或异步事务。

公开(公告)号：US6148357A

公开(公告)日：2000-11-14

申请号：US99228

申请日：1998-06-17

申请人： Dale E. Gulick ,  Larry D. Hewitt

发明人： Dale E. Gulick ,  Larry D. Hewitt

IPC分类号： G06F13/40 ,  G06F13/38

CPC分类号： G06F13/4027

摘要： An integrated circuit includes a central processing unit, a memory controller circuit for interfacing to system memory, and an interconnect bus controller for interfacing to an interconnect bus. The interconnect bus controller gives priority to transfer of asynchronous data during a first transfer mode and priority to transfer of isochronous data during a second transfer mode. A switch selectively couples the CPU, the memory controller circuit and the interconnect bus controller.

摘要翻译： 集成电路包括中央处理单元，用于与系统存储器接口的存储器控​​制器电路和用于与互连总线接口的互连总线控制器。 互连总线控制器在第一传送模式期间优先处理异步数据的传输，并且在第二传送模式期间优先传送同步数据。 开关选择性地耦合CPU，存储器控制器电路和互连总线控制器。

公开(公告)号：US07421525B2

公开(公告)日：2008-09-02

申请号：US10842296

申请日：2004-05-10

申请人： R. Stephen Polzin ,  Frederick D. Weber ,  Gerald R. Talbot ,  Larry D. Hewitt ,  Richard W. Reeves ,  Shwetal A. Patel ,  Ross V. La Fetra ,  Dale E. Gulick ,  Mark D. Hummel ,  Paul C. Miranda

发明人： R. Stephen Polzin ,  Frederick D. Weber ,  Gerald R. Talbot ,  Larry D. Hewitt ,  Richard W. Reeves ,  Shwetal A. Patel ,  Ross V. La Fetra ,  Dale E. Gulick ,  Mark D. Hummel ,  Paul C. Miranda

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F12/00 ,  G11C5/06

CPC分类号： G06F13/4243 ,  G06F12/0215 ,  G06F12/0862 ,  G06F13/1626 ,  G06F2212/6022

摘要： A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

摘要翻译： 一种系统，包括耦合到串行连接的存储器模块链的主机。 在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片的访问的存储器控​​制集线器。 存储器模块通过多个存储器链路串联地连接到主机。 每个存储器链路可以包括用于向主机传送事务的上行链路和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路。 上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。 存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。