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公开(公告)号：US07308607B2
公开(公告)日：2007-12-11
申请号：US10651388
申请日：2003-08-29
IPC分类号： G06F11/00
CPC分类号： G06F9/3851 , G06F9/3863
摘要： A multithreaded architecture having one or more checker circuits that operate on store operations that send data outside of a sphere of replication. Fault detection mechanisms used to check outputs from the sphere of replication are reused for checkpointing at the conclusion of an execution epoch.
摘要翻译： 具有一个或多个检查器电路的多线程架构，其操作于在复制范围之外发送数据的存储操作。 用于检查复制领域的输出的故障检测机制在执行时间结束时重新用于检查点。
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公开(公告)号：US06961781B1
公开(公告)日：2005-11-01
申请号：US09652322
申请日：2000-08-31
IPC分类号： G06F15/16 , G06F15/173 , H04L12/56
CPC分类号： H04L47/6265 , H04L45/302 , H04L45/60 , H04L47/50 , H04L47/522
摘要： A system and method is disclosed for reducing network message passing latency in a distributed multiprocessing computer system that contains a plurality of microprocessors in a computer network, each microprocessor including router logic to route message packets prioritized in importance by the type of message packet, age of the message packet, and the source of the message packet. The microprocessors each include a plurality of network input ports connected to corresponding local arbiters in the router. The local arbiters are each able to select a message packet from the message packets waiting at the associated network input port. Microprocessor input ports and microprocessor output ports in the microprocessor allow the exchange of message packets between hardware functional units in the microprocessor and between the microprocessors. The microprocessor input ports are similarly each coupled to corresponding local arbiters in the router. Each of the local arbiters is able to select a message packet among the message packets waiting at the microprocessor input port. Global arbiters in the router connected to the network output ports and microprocessor output ports select a message packet from message packets nominated by the local arbiters of the network input ports and microprocessor input ports. The local arbiters connected to each network input port or microprocessor input port will request service from a output port global arbiter for a message packet based on the message packet type if the message packet is ready to be dispatched.
摘要翻译： 公开了一种用于减少在计算机网络中包含多个微处理器的分布式多处理计算机系统中的网络消息传递延迟的系统和方法，每个微处理器包括路由器逻辑，用于路由消息分组的重要性优先于消息分组的类型， 消息包和消息包的来源。 微处理器各自包括连接到路由器中对应的本地仲裁器的多个网络输入端口。 本地仲裁器能够从相关联的网络输入端口等待的消息分组中选择一个消息包。 微处理器输入端口和微处理器输出端口允许在微处理器中的硬件功能单元和微处理器之间交换消息包。 微处理器输入端口类似地分别耦合到路由器中的对应的本地仲裁器。 每个本地仲裁器能够在等待在微处理器输入端口的消息包中选择一个消息包。 连接到网络输出端口和微处理器输出端口的路由器中的全局仲裁器从由网络输入端口和微处理器输入端口的本地仲裁器指定的消息分组中选择消息分组。 连接到每个网络输入端口或微处理器输入端口的本地仲裁器将根据消息分组类型从消息分组的输出端口全局仲裁器请求服务，如果消息分组准备好被分派。
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33.发明授权公开(公告)号：US06854075B2
公开(公告)日：2005-02-08
申请号：US09837995
申请日：2001-04-19
CPC分类号： G06F9/3834 , G06F9/383 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F11/141 , G06F11/1497
摘要： A simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. One thread is processed ahead of the other thread so that the instructions in one thread are processed through the processor's pipeline ahead of the corresponding instructions from the other thread. The thread, whose instructions are processed earlier, places its committed stores in a store queue. Subsequently, the second thread places its committed stores in the store queue. A compare circuit periodically scans the store queue for matching store instructions. If otherwise matching store instructions differ in any way (address or data), then a fault has occurred in the processing and the compare circuits initiates fault recovery. If comparison of the two instructions reveals they are identical, the compare circuit allows only a single store instruction to pass to the data cache or the system main memory. In this way, transient faults are detected with a minimum amount of hardware overhead and independent of differences in the actual order of program execution or differences in branch speculation.
摘要翻译： 同时和冗余线程的流水线处理器同时执行同一组指令，作为两个单独的线程提供容错。 一个线程在另一个线程之前被处理，使得一条线程中的指令在来自另一线程的相应指令之前通过处理器的管线进行处理。 其指令被更早处理的线程将其提交的存储放置在存储队列中。 随后，第二个线程将其提交的存储放入存储队列。 比较电路周期性地扫描存储队列以匹配存储指令。 否则匹配存储指令以任何方式（地址或数据）不同，则处理中发生故障，比较电路启动故障恢复。 如果两个指令的比较显示它们相同，则比较电路只允许单个存储指令传递到数据高速缓存或系统主存储器。 以这种方式，以最小量的硬件开销检测瞬态故障，并且独立于程序执行的实际顺序或分支推测的差异。
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34.发明授权Slack fetch to improve performance in a simultaneous and redundantly threaded processor 有权轻松抓取以提高同步和冗余线程处理器的性能公开(公告)号：US06757811B1
公开(公告)日：2004-06-29
申请号：US09584034
申请日：2000-05-30
IPC分类号： G06F900
CPC分类号： G06F9/3842 , G06F9/3851
摘要： A simultaneous and redundantly threaded, pipelined processor can execute the same set of instructions simultaneously as two separate threads to provide, for example, fault tolerance. One thread is processed ahead of the other thread thereby creating a “slack” between the two threads so that the instructions in one thread are processed through the processor's pipeline ahead of the corresponding instructions from the other thread. The thread, whose instructions are processed earlier, is called the “leading” thread. The other thread is the “trailing” thread. By setting the amount of slack appropriately, all or at least some of the cache misses or branch misspeculations encountered by the trailing thread can be resolved by the time the corresponding instructions from the trailing thread are fetched and processed through the pipeline. The invention, therefore, improves the performance of a fault tolerant, simultaneous and redundantly threaded processor.
摘要翻译： 同时且冗余的线程流水线处理器可以与两个单独的线程同时执行同一组指令，以提供例如容错。 一个线程在另一个线程之前被处理，从而在两个线程之间产生“松弛”，使得一条线程中的指令在来自另一线程的相应指令之前的处理器的管线处理。 其指令被更早处理的线程称为“主导”线程。 另一个线程是“尾随”线程。 通过适当地设置松弛量，可以在拖尾线程的相应指令通过流水线获取和处理的时间之后，解析尾随线程遇到的所有或至少一些缓存未命中或分支错误规则。 因此，本发明改进了容错，同时和冗余线程处理器的性能。
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35.发明授权
公开(公告)号：US5951657A
公开(公告)日：1999-09-14
申请号：US871145
申请日：1997-06-09
申请人： David A. Wood , Steven K. Reinhardt , Shubhendu S. Mukherjee , Babak Falsafi , Mark D. Hill , Robert W. Pfile
发明人： David A. Wood , Steven K. Reinhardt , Shubhendu S. Mukherjee , Babak Falsafi , Mark D. Hill , Robert W. Pfile
CPC分类号： G06F5/10 , G06F12/0802 , G06F12/0835
摘要： A device interface for communicating between a processor system and a separate device employs cacheable control registers, both to indicate the receipt of a message and to receive messages to be transmitted. The data structure of the cacheable control registers may be that of a queue, minimizing the need for routine handshaking signals to clear the queue after each message. Communication of queue pointers is minimized by the use of a shadow pointer relied on as long as adequate queue space exists and queue entry valid flags which are interpreted with alternate sense for each cycling through the queue.
摘要翻译： 用于在处理器系统和单独设备之间进行通信的设备接口使用可缓存的控制寄存器，以指示消息的接收和接收要发送的消息。 可缓存控制寄存器的数据结构可以是队列的数据结构，最小化对每个消息后的队列的常规握手信号的清除。 只要存在足够的队列空间和队列条目有效标志，队列指针的通信就可以通过使用依赖于的影子指针来最小化。
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36.发明授权Method and apparatus for detecting transient faults via dynamic binary translation 有权通过动态二进制翻译检测瞬态故障的方法和装置公开(公告)号：US08291394B2
公开(公告)日：2012-10-16
申请号：US13135712
申请日：2011-07-13
IPC分类号： G06F9/45
CPC分类号： G06F8/52 , G06F8/53 , G06F11/008
摘要： A method for detecting transient fault includes translating binary code to an intermediate language code. An instruction of interest in the intermediate language code is identified. Reliability instructions are inserted in the intermediate language code to validate values from the instruction of interest. The intermediate language code is translated to binary code. Other embodiments are described and claimed.
摘要翻译： 用于检测瞬态故障的方法包括将二进制代码转换为中间语言代码。 识别中间语言代码感兴趣的指令。 可靠性指令插入中间语言代码以验证感兴趣的指令中的值。 中间语言代码被翻译成二进制代码。 描述和要求保护其他实施例。
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公开(公告)号：US07954038B2
公开(公告)日：2011-05-31
申请号：US11648853
申请日：2006-12-29
IPC分类号： G11C29/00
CPC分类号： G06F11/0751 , G06F11/0721 , G06F11/1407
摘要： Methods and apparatus to efficiently detect faults are described. In an embodiment, an encoded value may be generated based on a portion of an instruction address and a portion of a corresponding result value. The encoded value may be used to determine whether an entry corresponding to the encoded value is absent from a screening storage unit. Other embodiments are also described.
摘要翻译： 描述了有效检测故障的方法和设备。 在一个实施例中，可以基于指令地址的一部分和相应结果值的一部分来生成编码值。 编码值可以用于确定与筛选存储单元是否不存在与编码值相对应的条目。 还描述了其它实施例。
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38.发明授权公开(公告)号：US07555703B2
公开(公告)日：2009-06-30
申请号：US10871430
申请日：2004-06-17
申请人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver , Michael J. Smith
发明人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver , Michael J. Smith
IPC分类号： G06F11/00
CPC分类号： G06F9/3865 , G06F11/10
摘要： A technique to reduce false error detection in microprocessors. A pi bit is propagated with an instruction through an instruction flow path. When a parity error is detected, the pi bit is set, instead of raising a machine check exception. Upon reaching a commit point, the processor can determine if the instruction was on a wrong path.
摘要翻译： 减少微处理器中的错误检测的技术。 通过指令流程路径，通过指令传播pi位。 当检测到奇偶校验错误时，设置pi位，而不是提高机器检查异常。 达到提交点后，处理器可以确定指令是否在错误的路径上。
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39.发明授权Method and apparatus for reducing false error detection in a redundant multi-threaded system 有权用于减少冗余多线程系统中的错误检测的方法和装置公开(公告)号：US07543221B2
公开(公告)日：2009-06-02
申请号：US10948813
申请日：2004-09-22
申请人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver , Michael J. Smith
发明人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver , Michael J. Smith
IPC分类号： G06F11/00
CPC分类号： G06F9/3865 , G06F11/10
摘要： A technique to reduce false error detection in microprocessors within a redundant multi-threaded computing environment. A pi bit is propagated with at least two instructions through an instruction flow path. Results of executing the instruction are compared to see if an error has occurred and if so, the pi bits are examined to determine which instruction contains the error.
摘要翻译： 一种在冗余多线程计算环境中减少微处理器中的错误检测的技术。 通过指令流程路径，使用至少两个指令来传播pi位。 比较执行指令的结果，看是否发生错误，如果是，则检查pi位，以确定哪个指令包含错误。
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40.发明授权Reducing false error detection in a microprocessor by tracking instructions neutral to errors 有权通过跟踪中性到错误的指令，减少微处理器中的错误检测公开(公告)号：US07386756B2
公开(公告)日：2008-06-10
申请号：US10871429
申请日：2004-06-17
CPC分类号： G06F11/0721 , G06F9/30145 , G06F9/30181 , G06F9/3865 , G06F11/0751 , G06F11/1052 , G06F11/1407
摘要： A technique to reduce false error detection in microprocessors by tracking instructions neutral to errors. As an instruction is decoded, an anti-pi bit is tagged to the decoded instruction. When a parity error is detected, an instruction queue first checks if the anti-pi bit is set. If the anti-pi bit is set, then instruction is neutral to errors, and the pi bit need not be set. Prefetch, branch predict hint and NOP are types of instructions that are neutral to errors.
摘要翻译： 通过跟踪中性到错误的指令来减少微处理器中的错误检测的技术。 当指令被解码时，反码比特被标记到解码指令。 当检测到奇偶校验错误时，指令队列首先检查反pi位是否被设置。 如果反pi位被置位，则指令对于错误是中性的，并且不需要设置pi位。 预取，分支预测提示和NOP是对错误中立的指令类型。
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