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    THREE PART SOURCE/DRAIN REGION STRUCTURE FOR TRANSISTOR
    34.
    发明申请
    THREE PART SOURCE/DRAIN REGION STRUCTURE FOR TRANSISTOR 有权

    公开(公告)号：US20210320207A1

    公开(公告)日：2021-10-14

    申请号：US16843421

    申请日：2020-04-08

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Haiting Wang ,  Judson R. Holt ,  Sipeng Gu

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02

    Abstract: A structure for a field-effect transistor includes a semiconductor body, a first gate structure extending over the semiconductor body, and a second gate structure extending over the semiconductor body. A recess is in the semiconductor body between the first and second gate structures. A three part source/drain region includes a pair of spaced semiconductor spacers in the recess; a first semiconductor layer laterally between the pair of semiconductor spacers; and a second semiconductor layer over the first semiconductor layer. The pair of spaced semiconductor spacers, the first semiconductor layer and the second semiconductor layer may all have different dopant concentrations.

    MULTI-LEVEL ISOLATION STRUCTURE
    35.
    发明申请
    MULTI-LEVEL ISOLATION STRUCTURE 有权

    公开(公告)号：US20210313321A1

    公开(公告)日：2021-10-07

    申请号：US16842075

    申请日：2020-04-07

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Haiting Wang ,  Sipeng Gu ,  Shesh Mani Pandey ,  Lixia Lei ,  Gregory Costrini

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8234

    Abstract: One illustrative device disclosed herein includes at least one fin structure and an isolation structure comprising a stepped upper surface comprising a first region and a second region. The first region has a first upper surface and the second region has a second upper surface, wherein the first upper surface is positioned at a first level and the second upper surface is positioned at a second level and wherein the first level is below the second level. In this illustrative example, the device also includes a gate structure comprising a first portion and a second portion, wherein the first portion of the gate structure is positioned above the first upper surface of the isolation structure and above the at least one fin structure and wherein the second portion of the gate structure is positioned above the second upper surface of the isolation structure.

    MEMORY DEVICE AND METHODS OF MAKING SUCH A MEMORY DEVICE
    36.
    发明申请
    MEMORY DEVICE AND METHODS OF MAKING SUCH A MEMORY DEVICE 有权

    公开(公告)号：US20210305495A1

    公开(公告)日：2021-09-30

    申请号：US16836434

    申请日：2020-03-31

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Yanping Shen ,  Haiting Wang ,  Sipeng Gu

    IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01L27/22

    Abstract: One illustrative memory cell disclosed herein includes at least one layer of insulating material having a first opening and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer includes a spacer opening. The memory cell also includes a bottom electrode positioned within the spacer opening, a memory state material positioned above an upper surface of the bottom electrode and above an upper surface of the internal sidewall spacer, and a top electrode positioned above the memory state material.

    LDMOS integrated circuit product
    37.
    发明授权
    LDMOS integrated circuit product 有权

    公开(公告)号：US11075298B2

    公开(公告)日：2021-07-27

    申请号：US16454238

    申请日：2019-06-27

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Jiehui Shu ,  Judson R. Holt ,  Sipeng Gu ,  Halting Wang

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/41 ,  H01L29/66 ,  H01L29/417

    Abstract: One illustrative integrated circuit product disclosed herein includes a gate structure positioned above a semiconductor substrate, a source region and a drain region, both of which include an epi semiconductor material, wherein at least a portion of the epi semiconductor material in the source and drain regions is positioned in the substrate. In this example, the IC product also includes an isolation structure positioned in the substrate between the source region and the drain region, wherein the isolation structure includes a channel-side edge and a drain-side edge, wherein the channel-side edge is positioned vertically below the gate structure and wherein a portion of the substrate laterally separates the isolation structure from the epi semiconductor material in the drain region.

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