公开(公告)号：US20060184746A1

公开(公告)日：2006-08-17

申请号：US11056679

申请日：2005-02-11

申请人： Guy Guthrie ,  Hugh Shen ,  William Starke ,  Derek Williams

发明人： Guy Guthrie ,  Hugh Shen ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F13/1605 ,  G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/reorder unit is full in which case the new snoop request is transmitted to a second unit configured to transmit a request to retry resending the new snoop request. Snoop requests have a higher priority than requests from processors and snoop requests are selected by the arbitration mechanism over processor requests unless the arbitration mechanism requests otherwise (“stall request”) to the stall/reorder unit. By snoop requests having a higher priority than processor requests, the number of snoop requests rejected is reduced. By having the arbitration mechanism issue a stall request, the processor will not be starved.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 监听请求被输入到停止/重新排序单元的第一可用锁存器中，除非停止/重新排序单元已满，在这种情况下，新的窥探请求被发送到被配置为发送重新发送新的窥探请求的请求的第二单元。 侦听请求具有比来自处理器的请求更高的优先级，并且仲裁机制通过处理器请求选择侦听请求，除非仲裁机制另请求（“停止请求”）到停止/重新排序单元。 通过具有比处理器请求更高优先级的侦听请求，减少了被拒绝的侦听请求的数量。 通过使仲裁机制发出停顿请求，处理器不会饿死。

公开(公告)号：US20060184743A1

公开(公告)日：2006-08-17

申请号：US11056673

申请日：2005-02-12

申请人： Guy Guthrie ,  William Starke ,  Derek Williams

发明人： Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/0831 ,  G06F12/127

摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss.

摘要翻译： 一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。 在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。

公开(公告)号：US20080098177A1

公开(公告)日：2008-04-24

申请号：US11956112

申请日：2007-12-13

申请人： Guy Guthrie ,  William Starke ,  Derek Williams ,  Philip Williams

发明人： Guy Guthrie ,  William Starke ,  Derek Williams ,  Philip Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542

摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

摘要翻译： 一种用于在具有上部存储器和下部存储器高速缓存的存储器层级的数据处理系统中的高速缓存管理的系统和方法。 较低的存储器高速缓存控制器访问一致性状态表以确定当从上部存储器高速缓存中的一个接收到转入请求时存在于下部存储器高速缓存中的高速缓存行的一致性状态的替换策略。 一致性状态表实现替换策略，其在从上部存储器高速缓存中拔出时，在包含在两个级别的存储器中的特定高速缓存行的上下存储器高速缓存之间保留更有价值的高速缓存一致性状态信息。

公开(公告)号：US20080040556A1

公开(公告)日：2008-02-14

申请号：US11835984

申请日：2007-08-08

申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。 第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。

公开(公告)号：US20070226423A1

公开(公告)日：2007-09-27

申请号：US11388001

申请日：2006-03-23

申请人： Ravi Arimilli ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： Ravi Arimilli ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0822 ,  G06F12/084

摘要： A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor core that indicates a target memory block to be initialized, a cache memory in the first coherency domain determines a coherency state of the target memory block with respect to the cache memory. In response to the determination, the cache memory selects a scope of broadcast of an initialization request identifying the target memory block. A narrower scope including the first coherency domain and excluding the second coherency domain is selected in response to a determination of a first coherency state, and a broader scope including the first coherency domain and the second coherency domain is selected in response to a determination of a second coherency state. The cache memory then broadcasts an initialization request with the selected scope. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value.

摘要翻译： 数据处理系统至少包括第一和第二相干域，每个域包括至少一个处理器核和存储器。 响应于指示要初始化的目标存储器块的处理器核心的初始化操作，第一相干域中的高速缓存存储器确定目标存储器块相对于高速缓冲存储器的一致性状态。 响应于该确定，高速缓存存储器选择识别目标存储器块的初始化请求的广播范围。 响应于第一相关性状态的确定而选择包括第一相关域并且排除第二相关性域的较窄范围，并且响应于确定第一相关性域的第一相关性域和第二相关域 第二一致性状态。 然后，高速缓冲存储器播放具有所选范围的初始化请求。 响应于初始化请求，将目标存储器块在数据处理系统的存储器内初始化为初始化值。

公开(公告)号：US20060236037A1

公开(公告)日：2006-10-19

申请号：US11109085

申请日：2005-04-19

申请人： Guy Guthrie ,  Aaron Sawdey ,  William Starke ,  Derek Williams

发明人： Guy Guthrie ,  Aaron Sawdey ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0811 ,  G06F12/0813 ,  G06F12/0831

摘要： At a first cache memory affiliated with a first processor core, an exclusive memory access operation is received via an interconnect fabric coupling the first cache memory to second and third cache memories respectively affiliated with second and third processor cores. The exclusive memory access operation specifies a target address. In response to receipt of the exclusive memory access operation, the first cache memory detects presence or absence of a source indication indicating that the exclusive memory access operation originated from the second cache memory to which the first cache memory is coupled by a private communication network to which the third cache memory is not coupled. In response to detecting presence of the source indication, a coherency state field of the first cache memory that is associated with the target address is updated to a first data-invalid state. In response to detecting absence of the source indication, the coherency state field of the first cache memory is updated to a different second data-invalid state.

摘要翻译： 在与第一处理器核心相关联的第一高速缓冲存储器处，通过将第一高速缓冲存储器耦合到分别隶属于第二和第三处理器核的第二和第三高速缓冲存储器的互连结构接收独占存储器存取操作。 独占内存访问操作指定目标地址。 响应于独占存储器访问操作的接收，第一高速缓存存储器检测是否存在指示来自第一高速缓存存储器的专用存储器访问操作的源指示由第一高速缓冲存储器通过专用通信网络耦合到 第三缓存存储器未被耦合。 响应于检测到源指示的存在，与目标地址相关联的第一高速缓冲存储器的一致性状态字段被更新为第一数据无效状态。 响应于检测到不存在源指示，将第一高速缓冲存储器的一致性状态字段更新为不同的第二数据无效状态。

公开(公告)号：US20060184747A1

公开(公告)日：2006-08-17

申请号：US11056721

申请日：2005-02-11

申请人： Guy Guthrie ,  William Starke ,  Derek Williams ,  Phillip Williams

发明人： Guy Guthrie ,  William Starke ,  Derek Williams ,  Phillip Williams

IPC分类号： G06F13/28 ,  G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0851

摘要： A cache, system and method for improving the snoop bandwidth of a cache directory. A cache directory may be sliced into two smaller cache directories each with its own snooping logic. By having two cache directories that can be accessed simultaneously, the bandwidth can be essentially doubled. Furthermore, a “frequency matcher” may shift the cycle speed to a lower speed upon receiving snoop addresses from the interconnect thereby slowing down the rate at which requests are transmitted to the dispatch pipelines. Each dispatch pipeline is coupled to a sliced cache directory and is configured to search the cache directory to determine if data at the received addresses is stored in the cache memory. As a result of slowing down the rate at which requests are transmitted to the dispatch pipelines and accessing the two sliced cache directories simultaneously, the bandwidth or throughput of the cache directory may be improved.

摘要翻译： 用于提高缓存目录的窥探带宽的缓存，系统和方法。 高速缓存目录可以分成两个较小的缓存目录，每个具有自己的侦听逻辑。 通过具有可以同时访问的两个缓存目录，带宽可以基本上加倍。 此外，当从互连接收到窥探地址时，“频率匹配器”可以将周期速度转移到较低速度，从而将请求发送到调度管线的速率减慢。 每个调度流水线被耦合到一个切片缓存目录，并被配置为搜索该高速缓存目录以确定该接收到的地址上的数据是否被存储在该高速缓冲存储器中。 作为将请求发送到调度管线的速度变慢并且同时访问两个分片缓存目录的结果，可以提高缓存目录的带宽或吞吐量。

公开(公告)号：US20060179253A1

公开(公告)日：2006-08-10

申请号：US11054841

申请日：2005-02-10

申请人： James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F2212/1016 ,  G06F2212/1048

摘要： A data processing system includes a memory system, a plurality of masters that issue requests for access to memory blocks within the memory system, a plurality of snoopers that provide partial responses to requests by the masters, and response logic that generates combined responses for the requests in response to the partial responses provided by the plurality of snoopers. The plurality masters includes a winning master that issues a request for a particular memory block, and the plurality of snoopers includes a protecting snooper that, in response to receipt of the request, provides a partial response and protects a transfer of coherency ownership of the particular memory block to the winning master until expiration of a protection window extension following receipt from the response logic of a combined response for the request.

摘要翻译： 数据处理系统包括存储器系统，发出对存储器系统内的存储器块的访问请求的多个主器件，提供对由主器件发出的请求的部分响应的多个监视器以及产生针对请求的组合响应的响应逻辑 响应于由多个窥探者提供的部分响应。 多个主人包括发出对特定存储块的请求的获胜主，并且多个窥探者包括保护窥探者，其响应于该请求的接收而提供部分响应并保护特定存储块的一致性所有权的转移 记忆块到获胜主机，直到从请求的组合响应的响应逻辑接收到保护窗口扩展之后到期。

公开(公告)号：US20060179250A1

公开(公告)日：2006-08-10

申请号：US11055301

申请日：2005-02-10

申请人： Guy Guthrie ,  William Starke ,  Derek Williams ,  Philip Williams

发明人： Guy Guthrie ,  William Starke ,  Derek Williams ,  Philip Williams

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542

摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

公开(公告)号：US20080091885A1

公开(公告)日：2008-04-17

申请号：US11956102

申请日：2007-12-13

申请人： Guy Guthrie ,  William Starke ,  Derek Williams ,  Philip Williams

发明人： Guy Guthrie ,  William Starke ,  Derek Williams ,  Philip Williams

IPC分类号： G06F13/00

CPC分类号： G06F12/0811 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/2542

摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.