公开(公告)号：US10424378B2

公开(公告)日：2019-09-24

申请号：US16073922

申请日：2016-02-24

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Le Zheng ,  John Paul Strachan

IPC: G11C13/00 ,  G11C11/16 ,  G11C11/22 ,  G11C29/50

Abstract: In one example in accordance with the present disclosure a control circuit is described. The control circuit includes a source following component to receive an input voltage and output a switching voltage. The circuit also includes an input leg of a current mirror coupled to the source following component. The input leg of the current mirror replicates the switching voltage to an output leg of the current mirror of a memristive bit cell. The circuit also includes a number of current control components. At least one of the current control components enforces a constant current through the source following component and other current control components maintain the input leg of the current mirror and the output leg of the current mirror at the same current.

公开(公告)号：US20190027217A1

公开(公告)日：2019-01-24

申请号：US16065771

申请日：2016-01-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： John Paul Strachan ,  Brent Buchanan ,  Le Zheng

IPC: G11C13/00 ,  G11C11/56

Abstract: In one example in accordance with the present disclosure a memristive array is described. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices.

公开(公告)号：US20180218771A1

公开(公告)日：2018-08-02

申请号：US15418040

申请日：2017-01-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Le Zheng ,  John Paul Strachan

IPC: G11C13/00 ,  G06F17/16

CPC classification number: G11C13/0069 ,  G06F17/16

Abstract: Examples disclosed herein relate to programming a first conductance of a first resistive memory device based on a first target value. The first conductance of the first resistive memory device is measured to determine a deviation of the first resistive memory device from the first target value. A second target value of a second resistive memory device is adjusted based on the deviation, and a second conductance of the second resistive memory device is programmed based on the adjusted second target value.

公开(公告)号：US20180121416A1

公开(公告)日：2018-05-03

申请号：US15336907

申请日：2016-10-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  Le Zheng ,  John Paul Strachan

IPC: G06F17/27

CPC classification number: G06F17/2735

Abstract: Comparators may be associated with dictionary entries. In one aspect, a dictionary entry may store a dictionary word. A register may store an input word. A comparator associated with the dictionary entry may compare the dictionary word and the input word. The comparison may be a bit by bit comparison. The comparator may output a signal indicating if the dictionary word is less than the input word, equal to the input word, or greater than the input word. The output may indicate indeterminate when the comparison is not yet complete.

公开(公告)号：US09934857B2

公开(公告)日：2018-04-03

申请号：US15228559

申请日：2016-08-04

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Le Zheng ,  Brent Buchanan ,  John Paul Strachan

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G11C15/046

Abstract: An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first data line and a second terminal that is selectively connected to a second data line via a first switching transistor. The bit cell may also include a second memristor that has a first terminal that is connected to a third data line and a second terminal that is selectively connected to a fourth data line via a second switching transistor. The bit cell may also include a first match-line transistor and a second match-line transistor that are connected in series between a first rail and a match line, with a gate of the first match-line transistor being connected to the second terminal of the first memristor, and a gate of the second match-line transistor being connected to the second terminal of the second memristor.

公开(公告)号：US09928904B2

公开(公告)日：2018-03-27

申请号：US15500046

申请日：2014-09-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  Le Zheng

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/003 ,  G11C11/1659 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79

Abstract: An example device in accordance with an aspect of the present disclosure includes a plurality of bit-cells coupled as an array. A bit-cell includes a first switch element, a second switch element, and a memory element coupled at a node. The plurality of bit-cells are coupled as the array based on a first bit-cell's memory element being coupled to a second bit-cell's node.

公开(公告)号：US09691483B1

公开(公告)日：2017-06-27

申请号：US15270087

申请日：2016-09-20

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Brent Buchanan ,  John Paul Strachan ,  Le Zheng

IPC: G11C15/00 ,  G06F3/06

CPC classification number: G11C15/00

Abstract: In one aspect, techniques for providing a banked content addressable memory (CAM) with counters are provided. A dictionary word may be divided into a plurality of banks. A counter may be associated with each bank of the plurality of banks. The counter may count the number of times a segment of an input word aligned with the bank does not match. A scheduler may schedule comparison of banks with higher probability of not matching before banks with lower probability of not matching. The probability of not matching may be based on the counters.