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    LOGIC CIRCUITRY PACKAGE
    35.
    发明申请
    LOGIC CIRCUITRY PACKAGE 有权

    公开(公告)号：US20220001673A1

    公开(公告)日：2022-01-06

    申请号：US16959394

    申请日：2019-10-25

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Daryl Eugene ANDERSON ,  James Michael GARDNER ,  Christopher Hans BAKKER

    IPC: B41J2/175

    Abstract: A replaceable print apparatus component includes a print material reservoir, a print material within the reservoir having a first print material level, and a logic circuitry package including an interface and a logic circuit. The logic circuit may receive, via the interface, a first calibration parameter and receive, via the interface, a first request corresponding to a first sensor ID associated with a second print material level above the first print material level. The logic circuit may transmit, via the interface, a first digital value in response to the first request and receive, via the interface, a second calibration parameter less than the first calibration parameter. The logic circuit may receive, via the interface, a second request corresponding to the first sensor ID, and transmit, via the interface, a second digital value in response to the second request. The second digital value is less than the first digital value.

    LOGIC CIRCUITRY PACKAGE
    36.
    发明申请
    LOGIC CIRCUITRY PACKAGE 有权

    公开(公告)号：US20210372840A1

    公开(公告)日：2021-12-02

    申请号：US16768650

    申请日：2019-10-25

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Michael W. CUMBIE ,  James Michael GARDNER ,  Scott A. LINN

    IPC: G01F23/24 ,  G01F23/00 ,  B41J2/175

    Abstract: A logic circuitry package includes an interface to communicate with a print apparatus logic circuit and at least one logic circuit including at least one heater and a temperature sensor. The at least one logic circuit is configured to receive, via the interface, a heater command to address the at least one heater. The at least one logic circuit is configured to receive, via the interface, subsequent to the heater command, a sensor command corresponding to a sensor ID to address the temperature sensor. The at least one logic circuit is configured to transmit, via the interface, a digital value in response to the sensor command. The digital value corresponds to a print material level of a print material within a reservoir.

    IDENTIFYING RANDOM BITS IN CONTROL DATA PACKETS
    38.
    发明申请
    IDENTIFYING RANDOM BITS IN CONTROL DATA PACKETS 有权

    公开(公告)号：US20210229430A1

    公开(公告)日：2021-07-29

    申请号：US16769396

    申请日：2019-02-06

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： John ROSSI ,  Scott A. LINN ,  James Michael GARDNER ,  Erik D. NESS

    IPC: B41J2/045

    Abstract: A fluid ejection controller interface includes input logic to receive control data packets and a first clock signal, each control data packet including a set of primitive data bits and a set of random bits, wherein the input logic identifies the random bits in the received control data packets to facilitate the creation of modified control data packets. The fluid ejection controller interface includes a clock signal generator to generate a second clock signal that is different than the first clock signal, and output logic to receive the modified control data packets, and output the modified control data packets to a fluid ejection controller of a fluid ejection device based on the second clock signal.

    LOGIC CIRCUITRY PACKAGE
    39.
    发明申请
    LOGIC CIRCUITRY PACKAGE 有权

    公开(公告)号：US20210221143A1

    公开(公告)日：2021-07-22

    申请号：US16768628

    申请日：2019-10-25

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： James Michael GARDNER ,  David B. NOVAK

    IPC: B41J2/175 ,  B29C64/259 ,  B33Y30/00

    Abstract: A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit and at least one logic circuit including a memory storing a reference parameter. The at least one logic circuit is configured to receive, via the interface, a first request sent to a first address to read the reference parameter; and transmit, via the interface, the reference parameter in response to the first request. The at least one logic circuit is configured to receive, via the interface, a second request sent to a second address to implement a task; and implement the task to output a digital value via the interface in response to the second request. The reference parameter corresponds to the digital value.

    LOGIC CIRCUITRY
    40.
    发明申请
    LOGIC CIRCUITRY 有权

    公开(公告)号：US20210221125A1

    公开(公告)日：2021-07-22

    申请号：US16771092

    申请日：2018-12-03

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Stephen D. PANSHIN ,  Jefferson P. WARD ,  Scott A. LINN ,  James Michael GARDNER

    IPC: B41J2/045

    Abstract: In an example, a logic circuitry package is configured to be addressable via a first address and at least one second address and comprises a first logic circuit. The first address may be an address for the first logic circuit, and the package may be configured such that, in response to a first command indicative of a first command time period sent to the first address, the package is accessible via at least one second address for a duration of the first command time period; and in response to a second command indicative of a second command time period sent to the first address, the first logic circuit is to, for a duration of the second command time period, disregard traffic sent to the first address.

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