公开(公告)号：US07977236B2

公开(公告)日：2011-07-12

申请号：US12476364

申请日：2009-06-02

Applicant: Hasan Nejad ,  Thomas A. Figura ,  Gordon A. Haller ,  Ravi Iyer ,  John Mark Meldrim ,  Justin Harnish

Inventor： Hasan Nejad ,  Thomas A. Figura ,  Gordon A. Haller ,  Ravi Iyer ,  John Mark Meldrim ,  Justin Harnish

IPC: H01L21/4763

CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823814 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897 ,  H01L29/4975 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.

Abstract translation: 为嵌入硅完全硅化提供了方法和结构。 在沟槽内提供硅。 在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。 示例性的混合物包括80％的镍和20％的钴。 尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。 在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

公开(公告)号：US07547559B2

公开(公告)日：2009-06-16

申请号：US11657725

申请日：2007-01-25

Applicant: Hasan Nejad ,  James G. Deak

Inventor： Hasan Nejad ,  James G. Deak

IPC: H01L21/00

CPC classification number: H01L27/222 ,  H01L43/12

Abstract: The present invention provides a method of forming an MRAM cell which minimizes the occurrence of electrical shorts during fabrication. A first conductor in a trench is provided in an insulating layer and an upper surface of the insulating layer and the first conductor is planarized. Then, a dielectric layer is deposited to a thickness slightly greater than the desired final thickness of a sense layer, which is formed later. The dielectric layer is then patterned and etched to form an opening for the cell shapes over the first conductor. Then, a permalloy is electroplated in the cell shapes to form the sense layer. The sense layer and dielectric layer are flattened and then a nonmagnetic tunnel barrier layer is deposited. Finally, the pinned layer is formed over the tunnel barrier layer.

Abstract translation: 本发明提供一种形成MRAM单元的方法，该方法在制造期间使电短路的发生最小化。 沟槽中的第一导体设置在绝缘层中，并且绝缘层和第一导体的上表面被平坦化。 然后，电介质层被沉积成稍大于稍后形成的感应层的期望最终厚度的厚度。 然后对电介质层进行图案化和蚀刻，以形成第一导体上的电池形状的开口。 然后，将坡莫合金电镀在电池形状中以形成感测层。 感应层和电介质层被平坦化，然后沉积非磁性隧道势垒层。 最后，在隧道势垒层上方形成钉扎层。

公开(公告)号：US20080180982A1

公开(公告)日：2008-07-31

申请号：US12010651

申请日：2008-01-28

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C5/06 ,  G11C11/00 ,  H01L21/00

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  G11C13/004 ,  G11C2013/0054 ,  H01L27/2481

Abstract: This invention relates to memory technology and new variations on memory array architecture to incorporate certain advantages from both cross-point and 1T-1Cell architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple memory cells, which can be stacked vertically above one another in a plurality of memory array layers arranged in a “Z” axis direction.

公开(公告)号：US07306954B2

公开(公告)日：2007-12-11

申请号：US10637096

申请日：2003-08-08

Applicant: Hasan Nejad ,  James G. Deak

Inventor： Hasan Nejad ,  James G. Deak

IPC: H01L21/8244

CPC classification number: H01L27/222 ,  G11C11/15 ,  H01L43/08 ,  H01L43/12

Abstract: MRAM structures employ the magnetic properties of layered magnetic and non-magnetic materials to read memory storage logic states. Improvements in switching reliability may be achieved by altering the shape of the layered magnetic stack structure. Forming recessed regions with sloped interior walls in an ILD layer prior to depositing the layered magnetic stack structure produces a significant advantage over the prior art by allowing a CMP process to be used to define the magnetic bit shapes. The sloped interior walls of the recessed regions, which is singular to the present invention, provide a unique formation and shaping of the magnetic stack structure, which may reduce the magnetic coupling effect between magnetic layers of the magnetic stack structure.

Abstract translation: MRAM结构采用分层磁性和非磁性材料的磁性来读取存储器存储逻辑状态。 可以通过改变分层磁堆栈结构的形状来实现开关可靠性的改进。 在沉积分层磁堆栈结构之前，在ILD层中形成具有倾斜内壁的凹陷区域通过允许使用CMP工艺来定义磁头形状而产生比现有技术更大的优点。 凹陷区域的倾斜内壁，对于本发明而言是单一的，提供了磁性堆叠结构的独特的形成和成形，这可以减小磁性堆叠结构的磁性层之间的磁耦合效应。

公开(公告)号：US20070105357A1

公开(公告)日：2007-05-10

申请号：US11614802

申请日：2006-12-21

Applicant: Hasan Nejad ,  Thomas Figura ,  Gordon Haller ,  Ravi Iyer ,  John Meldrim ,  Justin Harnish

Inventor： Hasan Nejad ,  Thomas Figura ,  Gordon Haller ,  Ravi Iyer ,  John Meldrim ,  Justin Harnish

IPC: H01L21/3205 ,  H01L23/48

CPC classification number: H01L21/823835 ,  H01L21/28097 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823814 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10897 ,  H01L29/4975 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.

Abstract translation: 为嵌入硅完全硅化提供了方法和结构。 在沟槽内提供硅。 在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。 示例性的混合物包括80％的镍和20％的钴。 尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。 在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

公开(公告)号：US07214621B2

公开(公告)日：2007-05-08

申请号：US11131994

申请日：2005-05-18

Applicant: Hasan Nejad ,  Gordon A. Haller ,  Thomas Arthur Figura ,  Ravi Iyer

Inventor： Hasan Nejad ,  Gordon A. Haller ,  Thomas Arthur Figura ,  Ravi Iyer

IPC: H01L21/8244

CPC classification number: H01L27/10894 ,  H01L27/10876 ,  H01L27/10897 ,  Y10S439/917

Abstract: The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.

Abstract translation: 本发明包括形成与半导体结构相关的器件的方法。 在示例性方法中，利用通常的处理步骤来形成完全硅化的凹陷阵列存取栅极和部分硅化的外围晶体管栅极。

公开(公告)号：US07209378B2

公开(公告)日：2007-04-24

申请号：US10925243

申请日：2004-08-25

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/00

CPC classification number: G11C11/16 ,  G11C5/02 ,  G11C11/22 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  H01L27/228 ,  H01L27/24

Abstract: A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.

Abstract translation: 存储器阵列架构在读取操作期间融合了交叉点和1T-1Cell架构的某些优点。 通过使用单个存取晶体管来控制多个堆叠列的存储单元的读取，利用了1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度 列设置在相应的堆叠存储层中。

公开(公告)号：US20070020774A1

公开(公告)日：2007-01-25

申请号：US11521289

申请日：2006-09-13

Applicant: Hasan Nejad

Inventor： Hasan Nejad

IPC: H01L21/00

CPC classification number: H01L27/222 ,  G11C11/16

Abstract: The invention includes a method of forming a magnetoresistive memory device having a memory bit stack. The stack includes a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. A first conductive line is proximate the stack and configured for utilization in reading information from the memory bit. The first conductive line is ohmically connecting with either the first or second magnetic layer. A second conductive line is spaced from the stack by a sufficient distance that the second conductive line is not ohmically connected to the stack, and is configured for utilization in writing information to the memory bit. The invention also includes methods of storing and retrieving information.

Abstract translation: 本发明包括形成具有存储器位堆栈的磁阻存储器件的方法。 该堆叠包括在第一和第二磁性层之间的第一磁性层，第二磁性层和非磁性层。 第一导线靠近堆叠并被配置为用于从存储器位读取信息。 第一导线与第一或第二磁性层的欧姆连接。 第二导线与叠层隔开足够的距离，使得第二导线不被欧姆连接到堆叠，并被配置为用于将信息写入存储器位。 本发明还包括存储和检索信息的方法。

公开(公告)号：US20060171224A1

公开(公告)日：2006-08-03

申请号：US11394233

申请日：2006-03-31

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C7/00

CPC classification number: G11C11/16 ,  G11C5/02 ,  G11C11/22 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  H01L27/228 ,  H01L27/24

Abstract: A memory array architecture incorporates certain advantages from both cross-point and 1T-1Cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1Cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of memory cells, each column being provided in a respective stacked memory layer.

Abstract translation: 存储器阵列架构在读取操作期间融合了交叉点和1T-1Cell架构的某些优点。 通过使用单个存取晶体管来控制多个堆叠列的存储单元的读取，利用了1T-1Cell架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度 列设置在相应的堆叠存储层中。

公开(公告)号：US20050226038A1

公开(公告)日：2005-10-13

申请号：US11142448

申请日：2005-06-02

Applicant: Hasan Nejad ,  Mirmajid Seyyedy

Inventor： Hasan Nejad ,  Mirmajid Seyyedy

IPC: G11C11/00 ,  G11C11/16

CPC classification number: H01L27/228 ,  G11C5/02 ,  G11C11/16

Abstract: This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Abstract translation: 本发明涉及一种在读取操作期间结合来自交叉点和1T-1MTJ架构的某些优点的MRAM阵列体系结构。 通过使用单个存取晶体管来控制1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度，以控制每个列的多个堆叠列的MRAM单元的读数 设置在相应的堆叠存储层中。