公开(公告)号：US20110085404A1

公开(公告)日：2011-04-14

申请号：US12923751

申请日：2010-10-06

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C8/12 ,  G11C8/06

CPC分类号： G11C5/063 ,  G11C5/02

摘要： The semiconductor memory device includes plural core chips that are allocated with different chip identification information from each other and an interface chip that controls the plural core chips. The interface chip receives address information to specify memory cells and commonly supplies a part of the address information as chip selection information for comparison with the chip identification information to the plural core chips. As a result, since the controller recognizes that an address space is simply enlarged, the same interface as that in the semiconductor memory device according to the related art can be used.

摘要翻译： 半导体存储器件包括分配有彼此不同的芯片识别信息的多个芯片芯片和控制多个芯片芯片的接口芯片。 接口芯片接收地址信息以指定存储器单元，并且通常将一部分地址信息作为芯片选择信息提供，以便与芯片识别信息进行比较以提供给多个核心芯片。 结果，由于控制器识别出地址空间被简单地放大，所以可以使用与根据现有技术的半导体存储器件相同的界面。

公开(公告)号：US07869973B2

公开(公告)日：2011-01-11

申请号：US11841286

申请日：2007-08-20

申请人： Hideyuki Yoko ,  Hiroki Fujisawa

发明人： Hideyuki Yoko ,  Hiroki Fujisawa

IPC分类号： G01R35/00

CPC分类号： H03F1/56 ,  H03F2200/366 ,  H03F2200/453 ,  H03F2200/456

摘要： To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT1 or ACT2 is activated, and a calibration operation is performed for either the first replica buffer or the second replica buffer. When a second calibration command ZQCL is issued, both of the control signals ACT1, ACT2 are activated and the calibration operation is performed for both the first replica buffer and the second replica buffer.

摘要翻译： 包括具有与构成输出缓冲器的上拉电路基本相同的电路配置的第一复制缓冲器和具有与构成输出缓冲器的下拉电路基本相同的电路配置的第二复制缓冲器。 当发出第一校准命令ZQCS时，控制信号ACT1或ACT2被激活，并且对于第一副本缓冲器或第二副本缓冲器执行校准操作。 当发出第二校准命令ZQCL时，控制信号ACT1，ACT2都被激活，并且对于第一副本缓冲器和第二副本缓冲器都执行校准操作。

公开(公告)号：US20070143052A1

公开(公告)日：2007-06-21

申请号：US11580902

申请日：2006-10-16

申请人： Hiroki Fujisawa ,  Hideyuki Yoko

发明人： Hiroki Fujisawa ,  Hideyuki Yoko

IPC分类号： G06F19/00

CPC分类号： H04L25/0278 ,  H04L25/12

摘要： Impedance adjusting transistors are once inactivated on every occasion of changing an impedance adjusting code. After restoring the potential to an initially set potential by once inactivating the impedance adjusting transistors, the state of the transistors is switched according to the impedance adjusting code. By starting the potential from the initially set potential at the time of switching the state of the transistors, no switching noise is generated. Since no switching noise is generated, a comparator always carries out stable comparison and judgment and thus there is obtained a calibration circuit that ensures stable outputs.

摘要翻译： 在改变阻抗调整码的每个场合，阻抗调整晶体管一旦失效。 通过一旦使阻抗调节晶体管钝化，将电位恢复到初始设定电位后，根据阻抗调整代码切换晶体管的状态。 通过在切换晶体管的状态时从初始设定电位开始电位，不产生开关噪声。 由于不产生开关噪声，所以比较器总是执行稳定的比较和判断，从而获得确保稳定输出的校准电路。