公开(公告)号：US08599641B2

公开(公告)日：2013-12-03

申请号：US12923801

申请日：2010-10-07

申请人： Hideyuki Yoko ,  Naohisa Nishioka ,  Chikara Kondo ,  Ryuji Takishita

发明人： Hideyuki Yoko ,  Naohisa Nishioka ,  Chikara Kondo ,  Ryuji Takishita

IPC分类号： G11C8/00

CPC分类号： G11C7/222 ,  G06F1/10 ,  G11C5/02 ,  G11C29/02 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50012 ,  H01L2224/16145 ,  H01L2924/01037 ,  H01L2924/01055 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/15311 ,  H01L2924/00

摘要： Each of the core chips includes a data output circuit that outputs read data to the interface chip in response to a read command, and an output timing adjustment circuit that equalizes the periods of time required between the reception of the read command and the outputting of the read data from the data output circuit among the core chips. With this arrangement, a sufficient latch margin for read data to be input can be secured on the interface chip side. Furthermore, as the output timing is adjusted on each core chip side, there is no need to prepare the same number of latch timing control circuits as the number of core chips on the interface chip side.

摘要翻译： 每个核心芯片包括数据输出电路，其响应于读取命令将读取数据输出到接口芯片;以及输出定时调整电路，其将接收到读取命令和输出读取命令之间所需的时间相等 从核心芯片中的数据输出电路读取数据。 通过这种布置，可以在接口芯片侧确保用于要输入的读取数据的足够的锁存余量。 此外，由于在每个芯片侧调整输出定时，因此不需要准备与接口芯片侧的芯片数相同数量的锁存定时控制电路。

公开(公告)号：US20120320654A1

公开(公告)日：2012-12-20

申请号：US13595824

申请日：2012-08-27

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C5/06

CPC分类号： G11C5/14 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4074 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/18 ,  H01L2924/00

摘要： A system that includes a first semiconductor chip, a second semiconductor chip, and a controller chip. The first semiconductor chip includes a first terminal, a second terminal, a first circuit electrically coupled to the second terminal, a second circuit electrically coupled to the first terminal and the first circuit, and a third circuit electrically coupled to the second circuit. The second semiconductor chip includes a third terminal, a fourth terminal, a fourth circuit electrically coupled to the fourth terminal, a fifth circuit electrically coupled to the third terminal and the fourth circuit, and a sixth circuit electrically coupled to the fifth circuit.

摘要翻译： 一种包括第一半导体芯片，第二半导体芯片和控制器芯片的系统。 第一半导体芯片包括第一端子，第二端子，电耦合到第二端子的第一电路，电耦合到第一端子和第一电路的第二电路，以及电耦合到第二电路的第三电路。 第二半导体芯片包括第三端子，第四端子，电耦合到第四端子的第四电路，电耦合到第三端子和第四电路的第五电路，以及电耦合到第五电路的第六电路。

公开(公告)号：US20120305917A1

公开(公告)日：2012-12-06

申请号：US13563650

申请日：2012-07-31

申请人： Hideyuki YOKO ,  Kayoko SHIBATA

发明人： Hideyuki YOKO ,  Kayoko SHIBATA

IPC分类号： H01L23/48 ,  H01L23/488

CPC分类号： H01L27/10897 ,  G11C5/04 ,  G11C5/063 ,  G11C29/12 ,  H01L22/22 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596

摘要： A semiconductor device includes a first semiconductor chip that includes a driver circuit, a second semiconductor chip that includes a receiver circuit and an external terminal, and a plurality of through silicon vias that connect the first semiconductor chip and the second semiconductor chip. The first semiconductor chip further includes an output switching circuit that selectively connects the driver circuit to any one of the through silicon vias, the second semiconductor chip further includes an input switching circuit that selectively connects the receiver circuit to any one of the through silicon vias and the external terminal, the input switching circuit includes tri-state inverters each inserted between the receiver circuit and an associated one of the through silicon vias and the external terminal, and the input switching circuit activates any one of the tri-state inverters.

摘要翻译： 半导体器件包括包括驱动电路的第一半导体芯片，包括接收器电路和外部端子的第二半导体芯片，以及连接第一半导体芯片和第二半导体芯片的多个通孔硅通孔。 第一半导体芯片还包括输出开关电路，其选择性地将驱动电路连接到任何一个通孔硅通孔，第二半导体芯片还包括输入开关电路，其选择性地将接收器电路连接到通孔硅通孔中的任一个， 外部端子，输入开关电路包括各自插入在接收器电路和通孔硅通孔和外部端子中的相关联的一个之间的三态反相器，并且输入开关电路激活三态反相器中的任何一个。

公开(公告)号：US20120195136A1

公开(公告)日：2012-08-02

申请号：US12929668

申请日：2011-02-07

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C8/18 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C11/4093 ,  G11C5/04 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/4082 ,  G11C29/702 ,  H01L2224/16145

摘要： A semiconductor device according to the present invention includes plural controlled chips CC0 to CC7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A13 to A15 and a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals A13 to A15 is transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals A13 to A15 reach the controlled chips earlier than the command signal ICMD.

摘要翻译： 根据本发明的半导体器件包括保持相互不同的层信息的多个受控芯片CC0至CC7，以及将共同层地址信号A13至A15和命令信号ICMD提供给受控芯片的控制芯片IF。 构成层地址信号A13至A15的每个位通过至少两个穿过硅通孔的硅通孔传输，每个通孔通过硅通孔从多个第一通孔中的每个受控芯片并联连接。 构成命令信号ICMD的每一位通过由输出开关电路和输入开关电路选择的硅通过一个相应的传输。 利用这种配置，层地址信号A13至A15比命令信号ICMD早到达受控芯片。

公开(公告)号：US20100177588A1

公开(公告)日：2010-07-15

申请号：US12687584

申请日：2010-01-14

申请人： Nakaba Kaiwa ,  Yutaka Ikeda ,  Hideyuki Yoko

发明人： Nakaba Kaiwa ,  Yutaka Ikeda ,  Hideyuki Yoko

IPC分类号： G11C8/18 ,  H03L7/00

CPC分类号： G11C8/18 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/2254

摘要： A calibration circuit includes replica buffers that have a substantially same circuit configuration as at least a part of an output buffer, an oscillator circuit that generates an internal clock in response to issuance of a calibration command, and a control circuit that controls an impedance of the replica buffers in synchronization with the internal clock. According to the present invention, because a calibration operation that does not depend on an external clock is performed, even when a frequency of the external clock is changed according to an operation mode or the like, it is possible to maintain a constant period of time given to a single adjustment step or a constant time required for a series of calibration operations.

摘要翻译： 校准电路包括具有与输出缓冲器的至少一部分基本相同的电路配置的复制缓冲器，响应于发出校准命令产生内部时钟的振荡器电路，以及控制电路 复制缓冲器与内部时钟同步。 根据本发明，由于执行不依赖于外部时钟的校准操作，即使当外部时钟的频率根据操作模式等而改变时，也可以保持恒定的时间段 给予一系列校准操作所需的单个调整步骤或恒定时间。

公开(公告)号：US20090108897A1

公开(公告)日：2009-04-30

申请号：US12257758

申请日：2008-10-24

申请人： Hideyuki YOKO ,  Ryuuji TAKISHITA

发明人： Hideyuki YOKO ,  Ryuuji TAKISHITA

IPC分类号： H03K3/356

CPC分类号： H03K3/012 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227 ,  H03K3/356113

摘要： A semiconductor device includes a power-supply control portion and a latch portion. The power-supply control portion supplies power to an internal circuit in response to an input signal synchronized with rising of clock. The latch portion latches the input signal in synchronization with falling of the clock and supplies the latched input signal to the internal circuit.

摘要翻译： 半导体器件包括电源控制部分和闩锁部分。 电源控制部分响应于与时钟的上升同步的输入信号向内部电路供电。 锁存部分与时钟的下降同步地锁存输入信号，并将锁存的输入信号提供给内部电路。

公开(公告)号：US20080046212A1

公开(公告)日：2008-02-21

申请号：US11841286

申请日：2007-08-20

申请人： Hideyuki YOKO ,  Hiroki FUJISAWA

发明人： Hideyuki YOKO ,  Hiroki FUJISAWA

IPC分类号： G06F19/00

CPC分类号： H03F1/56 ,  H03F2200/366 ,  H03F2200/453 ,  H03F2200/456

摘要： To include a first replica buffer that has substantially the same circuit configuration as a pull-up circuit which constitutes an output buffer and a second replica buffer that has substantially the same circuit configuration as a pull-down circuit which constitutes the output buffer. When a first calibration command ZQCS is issued, either a control signal ACT1 or ACT2 is activated, and a calibration operation is performed for either the first replica buffer or the second replica buffer. When a second calibration command ZQCL is issued, both of the control signals ACT1, ACT2 are activated and the calibration operation is performed for both the first replica buffer and the second replica buffer.

摘要翻译： 包括具有与构成输出缓冲器的上拉电路基本相同的电路配置的第一复制缓冲器和具有与构成输出缓冲器的下拉电路基本相同的电路配置的第二复制缓冲器。 当发出第一校准命令ZQCS时，控制信号ACT1或ACT2被激活，并且对于第一副本缓冲器或第二副本缓冲器执行校准操作。 当发出第二校准命令ZQCL时，控制信号ACT1，ACT2都被激活，并且对于第一复制缓冲器和第二副本缓冲器都执行校准操作。

公开(公告)号：US20070148796A1

公开(公告)日：2007-06-28

申请号：US11585108

申请日：2006-10-24

申请人： Masayuki Nakamura ,  Hideyuki Yoko

发明人： Masayuki Nakamura ,  Hideyuki Yoko

IPC分类号： H01L21/66 ,  H01L23/58 ,  G01R31/26

CPC分类号： H04L25/0278 ,  G11C7/1051 ,  G11C7/1057 ,  G11C2207/2254

摘要： AZQ calibration command internally generated from an external command different from a ZQ calbration command so as to automatically perform an additional ZQ calibration operation. A command interval between an imputted command and a next command is effectively employed to obtain a ZQ calibration period. The external command different from the ZQ calibration command is preferably a self-refreshed command. The addition of the ZQ calibration operation shortens intervals between ZQ calibration operations. Thus, it is possible to obtain a ZQ calibration circuit capable of performing a ZQ calibration operation more accurately.

摘要翻译： AZQ校准命令从内部由与ZQ calbration命令不同的外部命令生成，以便自动执行附加的ZQ校准操作。 有效地采用插补命令与下一命令之间的命令间隔来获得ZQ校准周期。 与ZQ校准命令不同的外部命令优选为自刷新命令。 添加ZQ校准操作可缩短ZQ校准操作之间的间隔。 因此，可以更精确地获得能够执行ZQ校准操作的ZQ校准电路。

公开(公告)号：US08400805B2

公开(公告)日：2013-03-19

申请号：US12929668

申请日：2011-02-07

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C5/00 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4093 ,  G11C5/04 ,  G11C7/1072 ,  G11C8/12 ,  G11C11/4082 ,  G11C29/702 ,  H01L2224/16145

摘要： A semiconductor device according to the present invention includes plural controlled chips CC0 to CC7 that hold mutually different layer information, and a control chip IF that supplies in common layer address signals A13 to A15 and a command signal ICMD to the controlled chips. Each bit that constitutes the layer address signals A13 to A15 is transmitted via at least two through silicon vias that are connected in parallel for each controlled chip out of plural first through silicon vias. Each bit that constitutes the command signal ICMD is transmitted via one corresponding through silicon via that is selected by an output switching circuit and an input switching circuit. With this configuration, the layer address signals A13 to A15 reach the controlled chips earlier than the command signal ICMD.

摘要翻译： 根据本发明的半导体器件包括保持相互不同的层信息的多个受控芯片CC0至CC7，以及将共同层地址信号A13至A15和命令信号ICMD提供给受控芯片的控制芯片IF。 构成层地址信号A13至A15的每个位通过至少两个穿过硅通孔的硅通孔传输，每个通孔通过硅通孔从多个第一通孔中的每个受控芯片并联连接。 构成命令信号ICMD的每一位通过由输出开关电路和输入开关电路选择的硅通过一个相应的传输。 利用这种配置，层地址信号A13至A15比命令信号ICMD早到达受控芯片。

公开(公告)号：US08274847B2

公开(公告)日：2012-09-25

申请号：US12964304

申请日：2010-12-09

申请人： Hideyuki Yoko

发明人： Hideyuki Yoko

IPC分类号： G11C16/04

CPC分类号： G11C5/14 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4074 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/18 ,  H01L2924/00

摘要： To provide a semiconductor system including a plurality of core chips and an interface chip that controls the core chips. Each of the core chips includes an internal voltage generating circuit. The interface chip includes an unused chip information holding circuit that stores therein unused chip information of the core chips. The core chips respectively receive the unused chip information from the unused chip information holding circuit. When the unused chip information indicates an unused state, the internal voltage generating circuits are inactivated, and when the unused chip information indicates a used state, the internal voltage generating circuits are activated. With this configuration, unnecessary power consumption by the unused chips is reduced.

摘要翻译： 提供包括多个核心芯片的半导体系统和控制核心芯片的接口芯片。 每个核心芯片包括内部电压产生电路。 接口芯片包括未使用的芯片信息保持电路，其存储芯芯的未使用的芯片信息。 核心芯片分别从未使用的芯片信息保持电路接收未使用的芯片信息。 当未使用的芯片信息表示未使用状态时，内部电压产生电路被去激活，并且当未使用的芯片信息指示使用状态时，内部电压产生电路被激活。 利用这种配置，可以减少未使用芯片的不必要的功耗。