公开(公告)号：US20080036006A1

公开(公告)日：2008-02-14

申请号：US11802281

申请日：2007-05-22

申请人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

发明人： Tetsuji Ueno ,  Hwa-sung Rhee ,  Ho Lee

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.

摘要翻译： 具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。 该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。 在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

公开(公告)号：US20060131656A1

公开(公告)日：2006-06-22

申请号：US11285978

申请日：2005-11-23

申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L29/94

CPC分类号： H01L29/7834 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628

摘要： A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.

摘要翻译： 提供互补金属氧化物半导体（CMOS）器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。 第一和第二栅极图案分别设置成跨越第一和第二有源区域。 第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧，并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。 第一升高的源极/漏极区域设置在第一有源区上，而第二升高的源极/漏极区域设置在第二有源区域上。 在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。 设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。 还提供了制造CMOS器件的方法。

公开(公告)号：US20060088968A1

公开(公告)日：2006-04-27

申请号：US11299447

申请日：2005-12-08

申请人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

发明人： Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee ,  Seung-Hwan Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.

摘要翻译： 使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。 将具有凹部的基板装入反应室。 将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。 选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

公开(公告)号：US20060038230A1

公开(公告)日：2006-02-23

申请号：US11207703

申请日：2005-08-19

申请人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee ,  Dong-Suk Shin ,  Seung-Hwan Lee

发明人： Tetsuji Ueno ,  Hwa-Sung Rhee ,  Ho Lee ,  Dong-Suk Shin ,  Seung-Hwan Lee

IPC分类号： H01L27/12 ,  H01L29/06

CPC分类号： H01L29/66636 ,  H01L29/045 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7834

摘要： A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.

公开(公告)号：US20060008961A1

公开(公告)日：2006-01-12

申请号：US11158978

申请日：2005-06-22

申请人： Seung-Hwan Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee

发明人： Seung-Hwan Lee ,  Dong-Suk Shin ,  Hwa-Sung Rhee ,  Tetsuji Ueno ,  Ho Lee

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/4975 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

摘要： Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is formed on sidewalls of the gate pattern. A selective epitaxial growth process is applied to form semiconductor layers on the gate pattern and on the active region at both sides of the gate pattern. In this case, a poly-crystalline semiconductor layer is formed on the gate pattern while single-crystalline semiconductor layers are concurrently formed on the active region at both sides of the gate pattern. The semiconductor layers are selectively etched to form a gate-reduced pattern and elevated source and drain regions. Respective desired thicknesses of the gate-reduced pattern and the elevated source and drain regions may be obtained using an etch selectivity between the poly-crystalline semiconductor layer and the single-crystalline semiconductor layer. A silicidation process is applied to the semiconductor substrate where the gate-reduced pattern is formed to simultaneously form a fully silicided metal gate electrode and elevated source and drain silicide layers.

公开(公告)号：US20070001690A1

公开(公告)日：2007-01-04

申请号：US10553064

申请日：2004-04-13

申请人： Tetsuji Ueno ,  Yoshihiro Hirata ,  Kazunori Okada ,  Kazunori Kawase

发明人： Tetsuji Ueno ,  Yoshihiro Hirata ,  Kazunori Okada ,  Kazunori Kawase

IPC分类号： G01R31/02

CPC分类号： G01R1/06733

摘要： It is an object of the present invention to provide a beam splitter providing a high-contrast image and preventing light from scattering, and a laser scanning microscope provided with the above, in which there is provided a high-quality probe coming in contact with an electrode pad of a semiconductor device, in which a foreign substance is not likely to attach, a configuration is not likely changed and a preferable electrical contact can be maintained for a long time. According to the present invention, a probe coming into contact with an electrode pad of a measurement object comprises a connection terminal part integrally formed and connected to a substrate, a contact part having a tapered configuration, and a supporting part which supports the contact part. The contact part extending from an end of the supporting part has a sectional configuration which shares at least one side face with the supporting part.

摘要翻译： 本发明的目的是提供一种提供高对比度图像并防止光散射的分束器，以及具有上述的激光扫描显微镜，其中提供了与 由于外部物质不易附着的半导体器件的电极焊盘，因此不会发生形态变化，并且能够长时间保持优选的电接触。 根据本发明，与测量对象的电极焊盘接触的探针包括一体地形成并连接到基板的连接端子部分，具有锥形构造的接触部分和支撑接触部分的支撑部分。 从支撑部的端部延伸的接触部具有与支撑部分共享至少一个侧面的截面构造。

公开(公告)号：US07432726B2

公开(公告)日：2008-10-07

申请号：US10553064

申请日：2004-04-13

申请人： Tetsuji Ueno ,  Yoshihiro Hirata ,  Kazunori Okada ,  Kazunori Kawase

发明人： Tetsuji Ueno ,  Yoshihiro Hirata ,  Kazunori Okada ,  Kazunori Kawase

IPC分类号： G01R31/02

CPC分类号： G01R1/06733

摘要： According to an embodiment, a probe coming into contact with an electrode pad of a measurement object comprises a connection terminal part integrally formed and connected to a substrate, a contact part having a tapered configuration, and a supporting part which supports the contact part. The contact part extending from an end of the supporting part has a sectional configuration which shares at least one side face with the supporting part.

摘要翻译： 根据实施例，与测量对象的电极焊盘接触的探针包括一体形成并连接到基板的连接端子部分，具有锥形构造的接触部分和支撑接触部分的支撑部件。 从支撑部的端部延伸的接触部具有与支撑部分共享至少一个侧面的截面构造。

公开(公告)号：US20060156970A1

公开(公告)日：2006-07-20

申请号：US11232955

申请日：2005-09-23

申请人： Shin Dong-Suk ,  Tetsuji Ueno ,  Lee Seung-Hwan ,  Lee Ho ,  Rhee Hwa-Sung

发明人： Shin Dong-Suk ,  Tetsuji Ueno ,  Lee Seung-Hwan ,  Lee Ho ,  Rhee Hwa-Sung

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： C30B25/18

摘要： Provided is an in-situ precleaning method for use in conjunction with epitaxial processes that utilizes temperatures at or below those typically utilized during the subsequent epitaxial deposition under pressure and ambient conditions suitable for inducing decomposition of semiconductor oxides, such as native oxides, from exposed semiconductor surfaces. The reduced temperature and the resulting quality of the cleaned semiconductor surfaces will tend to reduce the likelihood of temperature related issues such as unwanted diffusion, autodoping, slip, and other crystalline stress problems while simultaneously reducing the overall process time. The combination of pressure, ambient gas composition and temperature maintained within the reaction chamber are sufficient to decompose semiconductor oxides present on the substrate surface. For example, the reaction chamber may be operated so that the concentration of evolved oxygen within the reaction chamber is less than about 50%, or even less than 10%, of the equilibrium vapor pressure under the cleaning conditions.

摘要翻译： 提供了一种与外延工艺结合使用的原位预清洗方法，该外延工艺利用在随后的外延沉积期间通常利用的温度等于或低于在压力和环境条件下适合于从暴露的半导体分解半导体氧化物（例如天然氧化物）的环境条件下的温度 表面。 清洁的半导体表面的降低的温度和所得到的质量倾向于降低诸如不期望的扩散，自掺杂，滑移和其它结晶应力问题之类的温度相关问题的可能性，同时减少整个处理时间。 压力，环境气体组成和保持在反应室内的温度的组合足以分解存在于基板表面上的半导体氧化物。 例如，可以操作反应室，使得在清洁条件下，反应室内的放出的氧气的浓度小于平衡蒸汽压力的约50％，甚至小于10％。

公开(公告)号：US06777728B2

公开(公告)日：2004-08-17

申请号：US10329773

申请日：2002-12-27

申请人： Masashi Shima ,  Tetsuji Ueno ,  Yoshiki Sakuma ,  Shunji Nakamura

发明人： Masashi Shima ,  Tetsuji Ueno ,  Yoshiki Sakuma ,  Shunji Nakamura

IPC分类号： H01L2976

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L27/0922 ,  H01L29/1054 ,  H01L29/802

摘要： A semiconductor device includes a channel layer, a gate electrode formed on the channel layer, a p-type source region formed on a first side of the channel layer, and a p-type drain region formed on a second side of the channel layer. A heavy-hole band and a light-hole band are separated by compressive strain applied isotropically in an in-plane direction in the channel layer. A channel direction connecting the p-type source and drain regions is set substantially to a direction to maximize hole mobility in the channel layer.

摘要翻译： 半导体器件包括沟道层，形成在沟道层上的栅电极，形成在沟道层的第一侧上的p型源极区域和形成在沟道层的第二侧上的p型漏极区域。 重孔带和光孔带通过在通道层中的面内方向各向同性地施加的压缩应变来分离。 连接p型源极区域和漏极区域的沟道方向基本上设置成使沟道层中的空穴迁移率最大化的方向。