公开(公告)号：US07964468B2

公开(公告)日：2011-06-21

申请号：US12715323

申请日：2010-03-01

申请人： Hsiang-Lan Lung ,  Yi-Chou Chen

发明人： Hsiang-Lan Lung ,  Yi-Chou Chen

IPC分类号： H01L21/20

CPC分类号： H01L45/143 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683 ,  Y10T29/49117

摘要： A multi-level, phase change memory cell has first and second thermal isolation materials having different thermal conductivity properties situated in heat-conducting relation to first and second boundaries of the phase change material. Accordingly, when an electrical current is applied to raise the temperature of the memory material, heat is drawn away from the memory material asymmetrically along a line orthogonal to electric field lines between the electrodes.

摘要翻译： 多级相变存储器单元具有第一和第二热隔离材料，该材料具有不同的导热性质，其位于与相变材料的第一和第二边界的导热关系中。 因此，当施加电流以提高存储材料的温度时，沿着与电极之间的电场线正交的线不对称地将热量从存储材料拉出。

公开(公告)号：US07920415B2

公开(公告)日：2011-04-05

申请号：US12715686

申请日：2010-03-02

申请人： Hsiang-Lan Lung ,  Yi-Chou Chen

发明人： Hsiang-Lan Lung ,  Yi-Chou Chen

IPC分类号： G11C11/00

CPC分类号： G11C13/0061 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

摘要： A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for programming disclosed herein includes determining a data value for the memory cell, and applying a pulse pair to store the data value. The pulse pair includes an initial pulse having a pulse shape adapted to preset the phase change material in the memory cell to a normalizing resistance state, and a subsequent pulse having a pulse shape adapted to set the phase change material from the normalizing resistance state to a resistance corresponding to the determined data value.

摘要翻译： 包括包括相变材料的存储单元的存储器件与用于编程存储器件的方法一起被描述。 本文公开的编程方法包括确定存储单元的数据值，以及应用脉冲对来存储数据值。 所述脉冲对包括具有脉冲形状的初始脉冲，所述脉冲形状适于将所述存储器单元中的相变材料预设为归一化电阻状态，以及具有脉冲形状的后续脉冲，其适于将所述相变材料从所述归一化电阻状态设置为 对应于确定的数据值的电阻。

公开(公告)号：US20070258279A1

公开(公告)日：2007-11-08

申请号：US11825193

申请日：2007-07-03

申请人： Hsiang-Lan Lung ,  Yi-Chou Chen

发明人： Hsiang-Lan Lung ,  Yi-Chou Chen

IPC分类号： G11C5/06

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1675 ,  H01L45/1691

摘要： A memory cell comprises a chalcogenide random access memory (CRAM) cell and a CMOS circuit. The CMOS circuit accesses the CRAM cell. The CRAM cell has a cross-sectional area that is determined by a thin film process (e.g., a chalcogenide deposition thin film process) and by an iso-etching process. If desired, the chalcogenide structure may be implemented in series with a semiconductor device such as a diode or a selecting transistor. The diode drives a current through the chalcogenide structure. The selecting transistor drives a current through the chalcogenide structure when enabled by a voltage at a gate terminal of the selecting transistor. The selecting transistor has a gate terminal, a source terminal, and a drain terminal; the gate terminal may be operatively coupled to a word line of a memory array, the source terminal may be operatively coupled to a drive line of the memory array, and the drain terminal may be operatively coupled to a bit line of the memory array.

公开(公告)号：US07247511B2

公开(公告)日：2007-07-24

申请号：US11485241

申请日：2006-07-11

申请人： Hsiang-Lan Lung ,  Yi-Chou Chen

发明人： Hsiang-Lan Lung ,  Yi-Chou Chen

IPC分类号： H01L21/00 ,  H01L21/06 ,  H01L21/20 ,  H01L29/76 ,  H01L29/94

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1675 ,  H01L45/1691

摘要： A memory cell comprises a chalcogenide random access memory (CRAM) cell and a CMOS circuit. The CMOS circuit accesses the CRAM cell. The CRAM cell has a cross-sectional area that is determined by a thin film process (e.g., a chalcogenide deposition thin film process) and by an iso-etching process. If desired, the chalcogenide structure may be implemented in series with a semiconductor device such as a diode or a selecting transistor. The diode drives a current through the chalcogenide structure. The selecting transistor drives a current through the chalcogenide structure when enabled by a voltage at a gate terminal of the selecting transistor. The selecting transistor has a gate terminal, a source terminal, and a drain terminal; the gate terminal may be operatively coupled to a word line of a memory array, the source terminal may be operatively coupled to a drive line of the memory array, and the drain terminal may be operatively coupled to a bit line of the memory array.

摘要翻译： 存储单元包括硫族化物随机存取存储器（CRAM）单元和CMOS电路。 CMOS电路访问CRAM单元。 CRAM单元具有通过薄膜工艺（例如，硫族化物沉积薄膜工艺）和通过等蚀刻工艺确定的横截面积。 如果需要，硫族化物结构可以与诸如二极管或选择晶体管的半导体器件串联地实现。 二极管驱动通过硫族化物结构的电流。 当通过选择晶体管的栅极端子处的电压使能时，选择晶体管驱动通过硫族化物结构的电流。 选择晶体管具有栅极端子，源极端子和漏极端子; 栅极端子可以可操作地耦合到存储器阵列的字线，源极端子可操作地耦合到存储器阵列的驱动线，并且漏极端子可以可操作地耦合到存储器阵列的位线。

公开(公告)号：US20060157681A1

公开(公告)日：2006-07-20

申请号：US11378904

申请日：2006-03-17

申请人： Yi-Chou Chen ,  Hsiang-Lan Lung ,  Ruichen Liu

发明人： Yi-Chou Chen ,  Hsiang-Lan Lung ,  Ruichen Liu

IPC分类号： H01L29/04

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1691

摘要： A process for fabricating phase-change elements having ultra small cross-sectional areas for use in phase change memory cells specifically and in semiconductor devices generally in which pads are implemented to create horizontally aligned phase change elements is disclosed. The elements thus defined may be used within chalcogenide memory cells or other semiconductor devices.

摘要翻译： 公开了一种制造相变元件的方法，该相变元件具有特别用于相变存储器单元的超小横截面积，并且在半导体器件中通常实现了用于产生水平排列的相变元件的焊盘。 如此定义的元件可以用在硫族化物存储单元或其他半导体器件中。

公开(公告)号：US07038230B2

公开(公告)日：2006-05-02

申请号：US10752422

申请日：2004-01-06

申请人： Yi-Chou Chen ,  Hsiang-Lan Lung ,  Ruichen Liu

发明人： Yi-Chou Chen ,  Hsiang-Lan Lung ,  Ruichen Liu

IPC分类号： H01L47/00

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1691

摘要： A process for fabricating phase-change elements having ultra small cross-sectional areas for use in phase change memory cells specifically and in semiconductor devices generally in which pads are implemented to create horizontally aligned phase change elements is disclosed. The elements thus defined may be used within chalcogenide memory cells or other semiconductor devices.

公开(公告)号：US07968861B2

公开(公告)日：2011-06-28

申请号：US12130075

申请日：2008-05-30

申请人： Geoffrey W. Burr ,  Yi-Chou Chen ,  Hsiang-Lan Lung

发明人： Geoffrey W. Burr ,  Yi-Chou Chen ,  Hsiang-Lan Lung

IPC分类号： H01L45/00

CPC分类号： H01L45/122 ,  G11C13/0004 ,  G11C2213/55 ,  H01L45/06 ,  H01L45/1675

摘要： Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a resistance, an insulating layer disposed between the first and second phase change layers; and a third phase change layer having a resistance, and coupled to each of the first and second phase change layers, bridging the insulating layer and electrically coupling the first and second phase change layers, wherein the resistance of the third phase change layer is greater than both the resistance of the first phase change layer and the second phase change layer.

摘要翻译： 具有通过重叠薄膜形成的具有小的相变开关体积的薄膜相变存储器。 示例性实施例包括相变存储元件，包括具有电阻的第一相变层，具有电阻的第二相变层，设置在第一和第二相变层之间的绝缘层; 以及具有电阻的第三相变层，并且耦合到所述第一和第二相变层中的每一个，桥接所述绝缘层并电耦合所述第一和第二相变层，其中所述第三相变层的电阻大于 第一相变层和第二相变层的电阻。

公开(公告)号：US20100151652A1

公开(公告)日：2010-06-17

申请号：US12715323

申请日：2010-03-01

申请人： Hsiang Lan Lung ,  Yi-Chou Chen

发明人： Hsiang Lan Lung ,  Yi-Chou Chen

IPC分类号： H01L21/02

CPC分类号： H01L45/143 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683 ,  Y10T29/49117

摘要： A multi-level, phase change memory cell has first and second thermal isolation materials having different thermal conductivity properties situated in heat-conducting relation to first and second boundaries of the phase change material. Accordingly, when an electrical current is applied to raise the temperature of the memory material, heat is drawn away from the memory material asymmetrically along a line orthogonal to electric field lines between the electrodes.

摘要翻译： 多级相变存储器单元具有第一和第二热隔离材料，该材料具有不同的导热性质，其位于与相变材料的第一和第二边界的导热关系中。 因此，当施加电流以提高存储材料的温度时，沿着与电极之间的电场线正交的线不对称地将热量从存储材料拉出。

公开(公告)号：US07701759B2

公开(公告)日：2010-04-20

申请号：US11777195

申请日：2007-07-12

申请人： Hsiang-Lan Lung ,  Yi-Chou Chen

发明人： Hsiang-Lan Lung ,  Yi-Chou Chen

IPC分类号： G11C11/00

CPC分类号： G11C13/0061 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

摘要： A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for programming disclosed herein includes determining a data value for the memory cell, and applying a pulse pair to store the data value. The pulse pair includes an initial pulse having a pulse shape adapted to preset the phase change material in the memory cell to a normalizing resistance state, and a subsequent pulse having a pulse shape adapted to set the phase change material from the normalizing resistance state to a resistance corresponding to the determined data value.

摘要翻译： 包括包括相变材料的存储单元的存储器件与用于编程存储器件的方法一起被描述。 本文公开的编程方法包括确定存储单元的数据值，以及应用脉冲对来存储数据值。 所述脉冲对包括具有脉冲形状的初始脉冲，所述脉冲形状适于将所述存储器单元中的相变材料预设为归一化电阻状态，以及具有脉冲形状的后续脉冲，其适于将所述相变材料从所述归一化电阻状态设定为 对应于确定的数据值的电阻。

公开(公告)号：US20080186755A1

公开(公告)日：2008-08-07

申请号：US11777195

申请日：2007-07-12

申请人： Hsiang Lan Lung ,  Yi-Chou Chen

发明人： Hsiang Lan Lung ,  Yi-Chou Chen

IPC分类号： G11C11/00

CPC分类号： G11C13/0061 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

摘要： A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for programming disclosed herein includes determining a data value for the memory cell, and applying a pulse pair to store the data value. The pulse pair includes an initial pulse having a pulse shape adapted to preset the phase change material in the memory cell to a normalizing resistance state, and a subsequent pulse having a pulse shape adapted to set the phase change material from the normalizing resistance state to a resistance corresponding to the determined data value.

摘要翻译： 包括包括相变材料的存储单元的存储器件与用于编程存储器件的方法一起被描述。 本文公开的编程方法包括确定存储单元的数据值，以及应用脉冲对来存储数据值。 所述脉冲对包括具有脉冲形状的初始脉冲，所述脉冲形状适于将所述存储器单元中的相变材料预设为归一化电阻状态，以及具有脉冲形状的后续脉冲，其适于将所述相变材料从所述归一化电阻状态设置为 对应于确定的数据值的电阻。