公开(公告)号：US20090073756A1

公开(公告)日：2009-03-19

申请号：US12313487

申请日：2008-11-20

申请人： Hsu Kai Yang

发明人： Hsu Kai Yang

IPC分类号： G11C11/14 ,  G11C7/00 ,  H01S4/00

CPC分类号： G11C11/1697 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  Y10T29/49002

摘要： A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that include a MTJ element and a select switching device. A local word line is associated with one row of the plurality of spin-torque MRAM cells and is connected to a gate terminal of the select switching devices of the row of MRAM cells to control activation and deactivation. One gate voltage boosting circuit is placed between an associated global word line and an associated local word line. The gate voltage boosting circuits boost a voltage of a gate of the selected switching device during writing of a logical “1” to the MTJ element of a selected spin-torque MRAM cell.

摘要翻译： 栅极升压电路为自旋转矩MRAM单元的选择开关MOS晶体管的栅极提供升压，以防止通过自旋转矩MRAM单元的MTJ器件的编程电流减小。 自旋转矩MRAM单元阵列由包括MTJ元件和选择开关器件的自旋转矩MRAM单元组成。 本地字线与多个自旋扭矩MRAM单元的一行相关联，并且连接到MRAM单元行的选择开关器件的栅极端子以控制激活和去激活。 一个栅极升压电路放置在相关联的全局字线和相关的本地字线之间。 栅极升压电路在将逻辑“1”写入所选择的自旋转矩MRAM单元的MTJ元件时，提高所选择的开关器件的栅极的电压。

公开(公告)号：US06295226B1

公开(公告)日：2001-09-25

申请号：US09506155

申请日：2000-02-17

申请人： Hsu Kai Yang

发明人： Hsu Kai Yang

IPC分类号： G11C1604

CPC分类号： G11C16/0433 ,  H01L27/115

摘要： A semiconductor memory device includes an erase line, a common line, and a first transistor coupled between the conductive line and the common line. The memory device includes a plurality of memory cells and bit lines, each memory cell including a program line, a memory transistor, and a tunneling capacitor having a first node coupled to the floating gate. A second transistor is coupled between the program line and another node of the tunneling capacitor. An access transistor is coupled to the memory transistor and the bit line. The second transistor may be a depletion-type transistor, as may be the first transistor that is coupled to the erase line. The memory cell may also be implemented as a single-polysilicon memory structure.

摘要翻译： 半导体存储器件包括擦除线，公共线和耦合在导线与公共线之间的第一晶体管。 存储器件包括多个存储器单元和位线，每个存储器单元包括一个编程线，一个存储晶体管和一个具有耦合到浮动栅极的第一个结点的隧道电容器。 第二晶体管耦合在编程线和隧道电容器的另一个节点之间。 存取晶体管耦合到存储晶体管和位线。 第二晶体管可以是耗尽型晶体管，可以是耦合到擦除线的第一晶体管。 存储单元也可以被实现为单多晶硅存储器结构。

公开(公告)号：US20220134585A1

公开(公告)日：2022-05-05

申请号：US17399653

申请日：2021-08-11

申请人： Hsu Kai Yang ,  Luke Tzenmin Luangrath ,  Jerin Tzenjie Luangrath

发明人： Hsu Kai Yang ,  Luke Tzenmin Luangrath ,  Jerin Tzenjie Luangrath

IPC分类号： B26B19/04 ,  B26B19/20 ,  B26B19/38 ,  A45D24/36 ,  A45D24/10

摘要： A hair cutting device adapted for cutting one's own hair comprises a comb piece having teeth with smooth comb edges near open ends and sharp cutting edges near closed ends, a moving cutting arm with sharp cutting teeth in contact and rough alignment with the sharp cutting edges of the comb piece, capable of reciprocating sideways back and forth and cutting hair in conjunction with the sharp cutting edges of the comb piece, and a hair guard in close proximity along their lengths. The hair guard can be lowered to expose the sharp cutting edges of the comb piece and moving cutting arm to cut hair or raised above the sharp cutting edges to work as a comb.

公开(公告)号：US20110188305A1

公开(公告)日：2011-08-04

申请号：US12658228

申请日：2010-02-04

申请人： Hsu Kai Yang

发明人： Hsu Kai Yang

IPC分类号： G11C11/14 ,  G11C7/02 ,  G11C5/14

CPC分类号： G11C7/02 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

摘要： An array of SMT MRAM cells has a read reference circuit that provides a reference current that is the sum of a minimum current through a reference SMT MRAM cell programmed with a maximum resistance and a maximum current through an reference SMT MRAM cell programmed with a minimum resistance. The reference current forms an average reference voltage at the reference input of a sense amplifier for reading a data state from selected SMT MRAM cells of the array such that the reference SMT MRAM cells will not be disturbed during a read operation. The read reference circuit compensates for current mismatching in the reference current caused by a second order non matching effect.

摘要翻译： 一组SMT MRAM单元具有一个读取参考电路，该参考电流是通过编程具有最大电阻的参考SMT MRAM单元的最小电流和通过最小电阻编程的参考SMT MRAM单元的最大电流之和的总和 。 参考电流在读出放大器的参考输入处形成平均参考电压，用于从阵列的所选SMT MRAM单元读取数据状态，使得参考SMT MRAM单元在读取操作期间不被干扰。 读取参考电路补偿由二阶非匹配效应引起的参考电流中的电流失配。

公开(公告)号：US07986572B2

公开(公告)日：2011-07-26

申请号：US12583255

申请日：2009-08-17

申请人： Hsu Kai Yang

发明人： Hsu Kai Yang

IPC分类号： G11C7/00

CPC分类号： G11C11/1697 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002

摘要： Magnetic memory elements such as Phase Change RAM and Spin Moment Transfer MRAM require high programming currents. These high programming currents require high gate to source/drain voltages for the cell transistors controlling these programming currents, which can degrade the reliability of these cell transistors. This invention describes a circuit and method to write information into individual memory cells while minimizing the gate voltage stress in the cell transistors of the memory cells in which no information is being written. The circuit of this invention has a separately controllable word line voltage supply for each row of the memory array and a separately controllable voltage supply for each bit line of the memory array. During the write operation the voltage is raised for the word line of only one row of the array. The bit line voltages are then adjusted so that a 1 is written into the desired cells in that row and a 0 is written into the desired cells in that row.

摘要翻译： 诸如相变RAM和自旋转矩MRAM之类的磁存储元件需要高编程电流。 这些高编程电流对于控制这些编程电流的单元晶体管需要高的栅极到源极/漏极电压，这可能降低这些单元晶体管的可靠性。 本发明描述了一种将信息写入各个存储单元中的电路和方法，同时最小化其中不写入信息的存储单元的单元晶体管中的栅极电压应力。 本发明的电路具有针对存储器阵列的每一行的可单独控制的字线电压电源和用于存储器阵列的每个位线的单独可控的电压源。 在写入操作期间，只有阵列的一行的字线升高电压。 然后调整位线电压，使得将1写入该行中的期望单元，并将0写入该行中期望的单元。

公开(公告)号：US07977111B2

公开(公告)日：2011-07-12

申请号：US12009366

申请日：2008-01-18

申请人： Xizeng Shi ,  Pokang Wang ,  Hsu Kai Yang

发明人： Xizeng Shi ,  Pokang Wang ,  Hsu Kai Yang

IPC分类号： G01N25/18

CPC分类号： G01R33/098 ,  G01R33/1269 ,  Y10S436/806

摘要： A magnetic sensor for identifying small superparamagnetic particles bonded to a substrate contains a regular orthogonal array of MTJ cells formed beneath that substrate. A magnetic field imposed on the particle, perpendicular to the substrate, induces a magnetic field that has a component within the MTJ cells that is along the plane of the MTJ free layer. If that free layer has a low switching threshold, the induced field of the particle will create resistance changes in a group of MTJ cells that lie beneath it. These resistance changes will be distributed in a characteristic formation or signature that will indicate the presence of the particle. If the particle's field is insufficient to produce the free layer switching, then a biasing field can be added in the direction of the hard axis and the combination of this field and the induced field allows the presence of the particle to be determined.

摘要翻译： 用于识别结合到衬底的小超顺磁性颗粒的磁传感器包含在该衬底下面形成的MTJ电池的规则正交阵列。 垂直于衬底施加在颗粒上的磁场诱导磁场，该磁场在MTJ单元内具有沿着MTJ自由层的平面的分量。 如果自由层具有低切换阈值，则颗粒的感应场将在其下面的一组MTJ细胞中产生电阻变化。 这些电阻变化将分布在表征粒子存在的特征形成或特征中。 如果粒子的场不足以产生自由层切换，则可以在硬轴的方向上添加偏置场，并且该场与感应场的组合允许确定粒子的存在。

公开(公告)号：US07957183B2

公开(公告)日：2011-06-07

申请号：US12387537

申请日：2009-05-04

申请人： Hsu Kai Yang

发明人： Hsu Kai Yang

IPC分类号： G11C11/14

CPC分类号： G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1675 ,  Y10T29/41

摘要： An SMT MRAM device includes a plurality of SMT MRAM cells arranged in an array of rows and columns. Single bit lines connect the columns of the SMT MRAM cells for receiving an in-phase data signal. Source lines connect pairs of rows of the SMT MRAM cells for receiving an out-of-phase data signal. Out-of-phase switching devices are connected to the source lines for selectively transferring the out-of-phase signal to the at least one source lines. Column select transistors are connected to the single bit lines for transferring an in-phase data signal to a selected column of the SMT MRAM cells. A precharge circuit selectively charges or discharges the single bit lines. Ground switching devices selectively connect to the source lines to a ground reference voltage source. A method for programming a selected SMT MRAM cell within a provided SMT MRAM device is described.

摘要翻译： SMT MRAM器件包括以行和列阵列排列的多个SMT MRAM单元。 单位线连接SMT MRAM单元的列，用于接收同相数据信号。 源极线连接SMT MRAM单元的行对，用于接收异相数据信号。 异相开关器件连接到源极线，用于选择性地将异相信号传输到至少一个源极线。 列选择晶体管连接到单位线，用于将同相数据信号传送到SMT MRAM单元的选定列。 预充电电路选择性地对单个位线进行充电或放电。 接地开关器件有选择地将源极线连接到接地参考电压源。 描述了在所提供的SMT MRAM设备内对所选择的SMT MRAM单元进行编程的方法。

公开(公告)号：US20110002162A1

公开(公告)日：2011-01-06

申请号：US12459655

申请日：2009-07-06

申请人： Hsu Kai Yang

发明人： Hsu Kai Yang

IPC分类号： G11C11/14 ,  G11C7/00

CPC分类号： G11C13/0004 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

摘要： This invention describes a circuit and method to limit the stress caused by gate voltages required to write a one or zero in magnetic memory elements using the Giant magneto-resistive effect, such as Phase Change RAM and Spin Moment Transfer MRAM, sometimes referred to as Spin Torque Transfer MRAM, which require high programming currents. The circuit and method selects one cell at a time for writing a one or a zero, different voltages to write a one or a zero, and a precharge circuit to limit the stress on non selected cells.

摘要翻译： 本发明描述了一种电路和方法，用于限制由使用巨磁阻效应的磁存储元件中写入一个或零所需的栅极电压引起的应力，例如相变RAM和自旋瞬时转移MRAM，有时称为自旋 需要高编程电流的转矩MRAM。 电路和方法一次选择一个单元，用于写入一个或零个不同的电压以写入一个或者零，以及预充电电路来限制非选择的单元上的应力。

公开(公告)号：US20100332900A1

公开(公告)日：2010-12-30

申请号：US12456923

申请日：2009-06-24

申请人： Hsu Kai Yang

发明人： Hsu Kai Yang

IPC分类号： G06F11/14 ,  G06F12/02

CPC分类号： G06F11/106 ,  G06F11/1096 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/46

摘要： A data scrubbing apparatus corrects disturb data errors occurring in an array of memory cells such as SMT MRAM cells. The data scrubbing apparatus receives an error indication that an error has occurred during a read operation of a grouping of memory cells within the array of memory cells. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data. Based on a scrub threshold value, the data scrubbing apparatus writes the corrected data back after a specific number of errors. The data scrubbing apparatus may further suspend writing back during a writing of data. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.

摘要翻译： 数据擦除装置校正在诸如SMT MRAM单元的存储单元阵列中发生的干扰数据错误。 数据擦除装置接收在存储器单元阵列内的一组存储器单元的读取操作期间发生错误的错误指示。 数据擦除装置可以生成描述要擦除的存储器单元的位置的地址。 然后，数据擦除装置命令存储器单元阵列回写校正的数据。 基于擦除阈值，数据擦除装置在经过特定数量的错误之后写入校正后的数据。 数据擦除装置可以在写入数据期间进一步中止写回。 在校正数据的回写期间，数据擦除装置在外部提供忙指示符。

公开(公告)号：US20100277974A1

公开(公告)日：2010-11-04

申请号：US12387537

申请日：2009-05-04

申请人： Hsu Kai Yang

发明人： Hsu Kai Yang

IPC分类号： G11C11/14 ,  G11C7/00 ,  H01L21/00 ,  G11C11/416

CPC分类号： G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1675 ,  Y10T29/41

摘要： An SMT MRAM device includes a plurality of SMT MRAM cells arranged in an array of rows and columns. Single bit lines connect the columns of the SMT MRAM cells for receiving an in-phase data signal. Source lines connect pairs of rows of the SMT MRAM cells for receiving an out-of-phase data signal. Out-of-phase switching devices are connected to the source lines for selectively transferring the out-of-phase signal to the at least one source lines. Column select transistors are connected to the single bit lines for transferring an in-phase data signal to a selected column of the SMT MRAM cells. A precharge circuit selectively charges or discharges the single bit lines. Ground switching devices selectively connect to the source lines to a ground reference voltage source. A method for programming a selected SMT MRAM cell within a provided SMT MRAM device is described.

摘要翻译： SMT MRAM器件包括以行和列阵列排列的多个SMT MRAM单元。 单位线连接SMT MRAM单元的列，用于接收同相数据信号。 源极线连接SMT MRAM单元的行对，用于接收异相数据信号。 异相开关器件连接到源极线，用于选择性地将异相信号传输到至少一个源极线。 列选择晶体管连接到单位线，用于将同相数据信号传送到SMT MRAM单元的选定列。 预充电电路选择性地对单个位线进行充电或放电。 接地开关器件选择性地将源极线连接到接地参考电压源。 描述了在所提供的SMT MRAM设备内对所选择的SMT MRAM单元进行编程的方法。