公开(公告)号：US07479425B2

公开(公告)日：2009-01-20

申请号：US11039430

申请日：2005-01-20

申请人： Chew Hoe Ang ,  Dong Kyun Sohn ,  Liang Choo Hsia

发明人： Chew Hoe Ang ,  Dong Kyun Sohn ,  Liang Choo Hsia

IPC分类号： H01L21/76

CPC分类号： H01L29/513 ,  H01L21/28282 ,  H01L29/792

摘要： Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking layer preferably comprised of a lower hafnium oxide storage layer and an upper oxide storage layer. We form a gate electrode over the top blocking layer. We pattern the layers to form a gate structure and form source/drain regions to complete the memory device. In a second example embodiment, we form a floating gate non-volatile memory device comprised of: a bottom tunnel layer comprised essentially of silicon oxide; a charge storage layer comprised of a tantalum oxide; a top blocking layer comprised essentially of silicon oxide; and a gate electrode. The embodiments also comprise anneals and nitridation steps.

摘要翻译： 浮栅非易失性存储器件的制造结构和方法。 在第一示例性实施例中，我们形成由较低氧化物隧道层和上部氧化铪隧道层组成的底部隧道层; 电荷存储层，其由氧化钽和顶部阻挡层组成，其优选由下部氧化铪存储层和上部氧化物存储层组成。 我们在顶部阻挡层上形成栅电极。 我们对这些层进行图案化以形成栅极结构并形成源极/漏极区域以完成存储器件。 在第二示例实施例中，我们形成浮栅非易失性存储器件，其包括：基本上由氧化硅组成的底部隧道层; 电荷存储层，由钽氧化物构成; 基本上由氧化硅组成的顶部阻挡层; 和栅电极。 实施例还包括退火和氮化步骤。

公开(公告)号：US07256084B2

公开(公告)日：2007-08-14

申请号：US11122667

申请日：2005-05-04

申请人： Khee Yong Lim ,  Wenhe Lin ,  Chung Woh Lai ,  Yong Meng Lee ,  Liang Choo Hsia ,  Young Way Teh ,  John Sudijono ,  Wee Leng Tan ,  Hui Peng Koh

发明人： Khee Yong Lim ,  Wenhe Lin ,  Chung Woh Lai ,  Yong Meng Lee ,  Liang Choo Hsia ,  Young Way Teh ,  John Sudijono ,  Wee Leng Tan ,  Hui Peng Koh

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864

摘要： An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.

摘要翻译： 示例性方法实施例形成在PFET和NFET区域上在衬底上产生拉伸应力的间隔物。 我们形成PFET和NFET栅极，并在PFET和NFET栅极上形成拉伸间隔物。 我们将第一离子注入拉伸的PFET间隔物中以形成中和的应力PFET间隔物。 中和的应力PFET间隔物减轻了由衬底上的拉伸应力间隔物产生的拉伸应力。 这提高了设备​​性能。

公开(公告)号：US07094669B2

公开(公告)日：2006-08-22

申请号：US10910499

申请日：2004-08-03

申请人： Xiaomei Bu ,  Alex See ,  Tae Jong Lee ,  Fan Zhang ,  Yeon Kheng Lim ,  Liang Choo Hsia

发明人： Xiaomei Bu ,  Alex See ,  Tae Jong Lee ,  Fan Zhang ,  Yeon Kheng Lim ,  Liang Choo Hsia

IPC分类号： H01L21/46 ,  H01L21/78 ,  H01L21/301 ,  H01L21/76 ,  H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.

公开(公告)号：US07084025B2

公开(公告)日：2006-08-01

申请号：US10885855

申请日：2004-07-07

申请人： Timothy Wee Hong Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

发明人： Timothy Wee Hong Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L21/305 ,  H01L21/4763

CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L21/28079 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/66545

摘要： A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers. The spacers are used as masks for the LDD Implant. The space between the PLDD regions is preferably larger that the space between the NLDD regions because of the wider PMOS spacers. The PLDD tends to diffuse readily more than NLDD due to the dopant being small and light (i.e. Boron). The wider spacer between the PMOS regions improves device performance by improving the short channel effects for PMOS. In addition, the oxidization of the sacrificial gates allows trimming of sacrificial gates thus extending the limitation of lithography. Another feature of an embodiment is that a portion of the initial pad oxide is removed, thus reducing the amount of undercut created during the channel oxide strip for the dummy gate process. This would improve on the gate overlap capacitance for a T-gate transistor. In a second embodiment, two metal gates with different work functions are formed.

摘要翻译： 使用替换栅极形成FET的工艺。 一个示例特征是使PMOS牺牲栅极比NMOS牺牲栅极窄。 PMOS栅极优选用Ge注入以增加被氧化形成PMOS间隔物的多晶牺牲栅极的量。 间隔件用作LDD植入物的掩模。 PLDD区域之间的间隔优选比由于较宽的PMOS间隔物而在NLDD区域之间的间隔更大。 由于掺杂剂小且轻（即硼），PLDD容易从NLDD扩散更多。 PMOS区域之间的较宽间隔通过改善PMOS的短沟道效应来提高器件性能。 此外，牺牲栅极的氧化允许修剪牺牲栅极，从而延长了光刻的限制。 一个实施例的另一个特征是初始衬垫氧化物的一部分被去除，从而减少了在用于虚拟栅极处理的沟道氧化物带期间产生的底切的量。 这将提高T栅极晶体管的栅极重叠电容。 在第二实施例中，形成具有不同功函数的两个金属栅极。

公开(公告)号：US06762085B2

公开(公告)日：2004-07-13

申请号：US10262169

申请日：2002-10-01

申请人： Jia Zhen Zheng ,  Soh Yun Siah ,  Liang Choo Hsia ,  Eng Hua Lim ,  Simon Chooi ,  Chew Hoe Ang

发明人： Jia Zhen Zheng ,  Soh Yun Siah ,  Liang Choo Hsia ,  Eng Hua Lim ,  Simon Chooi ,  Chew Hoe Ang

IPC分类号： H01L218238

CPC分类号： H01L29/66598 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864

摘要： A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertical spacer component located on the sides of the gate structure, and with horizontal spacer components located on the surface of the semiconductor substrate with a thick horizontal spacer component located adjacent to the gate structures, while a thinner horizontal spacer component is located adjacent to the thicker horizontal spacer component. After formation of a block out shape in a PMOS region of the CMOS device, a high angle implantation procedure is used to form a P type halo region in a top portion of the NMOS region, followed by another implantation procedure performed at lower implant angles, resulting in an N type LDD region in a portion of the NMOS region underlying the thicker horizontal spacer component, and resulting in an N type heavily doped source/drain region in a portion of the NMOS underlying the thinner horizontal spacer component. Another block out shape, and another series of similar implantation procedures is performed to create the halo, LDD and source/drain regions in the PMOS region. After formation of a photoresist block out shape on specific CMOS regions, a composite insulator spacer is formed on the sides of gate structures not covered by the photoresist shape, followed by formation of metal silicide on the gate structures and source/drain regions not covered by the photoresist block out shape.

摘要翻译： 已经开发了由于光刻掩模程序的减少而制造具有降低的处理成本的CMOS器件的方法。 该方法特征是在栅极结构的侧面上形成L形氧化硅间隔物，其中垂直间隔件部件位于栅极结构的侧面，并且水平间隔件部件位于半导体衬底的表面上，具有厚的水平间隔件 位于邻近门结构的位置，而较薄的水平间隔件组件位于较厚的水平间隔件部件附近。 在CMOS器件的PMOS区域中形成块状形状之后，使用高角度注入工艺在NMOS区域的顶部形成P型卤素区域，随后以较低的注入角度进行另一种注入工艺， 导致在较厚的水平间隔器部件下面的NMOS区域的一部分中的N型LDD区域，并且导致在较薄的水平间隔器部件下面的NMOS的一部分中的N型重掺杂的源极/漏极区域。 执行另一个块状形状，并且进行另一系列相似的注入工艺以在PMOS区域中产生卤素，LDD和源极/漏极区域。 在特定CMOS区域上形成光致抗蚀剂阻挡形状之后，在未被光致抗蚀剂形状覆盖的栅极结构的侧面上形成复合绝缘体间隔物，然后在栅极结构和未被覆盖的源极/漏极区域上形成金属硅化物 光致抗蚀剂阻挡形状。

公开(公告)号：US08572524B2

公开(公告)日：2013-10-29

申请号：US11943591

申请日：2007-11-21

申请人： Wenzhan Zhou ,  Liang Choo Hsia ,  Meisheng Zhou ,  Zheng Zou

发明人： Wenzhan Zhou ,  Liang Choo Hsia ,  Meisheng Zhou ,  Zheng Zou

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： An optical proximity correction (OPC) model incorporates inline process variation data. OPC is performed by adjusting an input mask pattern with a mask bias derived from the OPC model to correct errors in the input mask pattern.

摘要翻译： 光学邻近校正（OPC）模型包含在线过程变化数据。 通过使用从OPC模型导出的掩模偏差调整输入掩模图案来校正输入掩模图案中的错误来执行OPC。

公开(公告)号：US08293545B2

公开(公告)日：2012-10-23

申请号：US11927658

申请日：2007-10-29

申请人： Hai Cong ,  Yan Shan Li ,  Chun Hui Low ,  Yelehanka Ramachandramurthy Pradeep ,  Liang Choo Hsia

发明人： Hai Cong ,  Yan Shan Li ,  Chun Hui Low ,  Yelehanka Ramachandramurthy Pradeep ,  Liang Choo Hsia

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L23/58 ,  H01L29/10

CPC分类号： H01L23/585 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Test structures including test trenches are used to define critical dimension of trenches in a via level of an integrated circuit to produce substantially the same depth. The trenches are formed at the periphery of the IC to serve as guard rings.

摘要翻译： 包括测试沟槽的测试结构用于定义集成电路的通孔级中的沟槽的临界尺寸，以产生基本上相同的深度。 沟槽形成在IC的外围，用作保护环。

公开(公告)号：US08293544B2

公开(公告)日：2012-10-23

申请号：US12220792

申请日：2008-07-28

申请人： Debora Chyiu Hyia Poon ,  Alex Kh See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Debora Chyiu Hyia Poon ,  Alex Kh See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/00

CPC分类号： H01L27/088 ,  H01L27/0211

摘要： A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

摘要翻译： 制造半导体器件的方法（和半导体器件）利用热接近校正（TPC）技术来减少退火期间热变化的影响。 在实际制造之前，确定集成电路设计中感兴趣的位置（例如，晶体管），并且定义该位置周围的有效热区。 用于在该区域内制造的结构的热性质被用于计算在给定的退火过程中在感兴趣的位置将实现的估计温度。 如果估计温度低于或高于预定目标温度（或范围），则执行TPC。 可以执行各种TPC技术，例如在感兴趣的位置添加虚拟单元和/或改变要制造的结构的尺寸（导致经修改的热校正设计，以抑制由热变化引起的器件性能的局部变化 在退火期间。

公开(公告)号：US08289508B2

公开(公告)日：2012-10-16

申请号：US12621510

申请日：2009-11-19

申请人： Victor Seng Keong Lim ,  Rachel Yie Fang Wai ,  Fang Hong Gn ,  Liang Choo Hsia

发明人： Victor Seng Keong Lim ,  Rachel Yie Fang Wai ,  Fang Hong Gn ,  Liang Choo Hsia

IPC分类号： G01N21/00

CPC分类号： H01L22/12

摘要： A method of forming a device is disclosed. The method includes providing a substrate and processing a layer of the device on the substrate. The layer is inspected with an inspection tool for defects. The inspection tool is programmed with an inspection recipe determined from studying defects programmed into the layer at known locations.

摘要翻译： 公开了一种形成装置的方法。 该方法包括提供衬底并在衬底上处理器件的一层。 该层用检查工具检查缺陷。 检查工具用从在已知位置处编程到层中的缺陷来确定的检查配方来编程。

公开(公告)号：US07710182B2

公开(公告)日：2010-05-04

申请号：US12175464

申请日：2008-07-18

申请人： Hung Chang Yu ,  Fei Xu ,  Liang Choo Hsia

发明人： Hung Chang Yu ,  Fei Xu ,  Liang Choo Hsia

IPC分类号： H03L5/00

CPC分类号： H03K3/356182 ,  H03K3/012

摘要： The present invention relates to integrated circuits. In particular, it relates to an IC comprising a receiving stage for receiving an input signal, an output stage for generating an output signal having a larger voltage range than the input signal and a level shifter. Embodiments of the invention provide a structure and a method for fabricating the IC wherein the level shifter is incorporated within the IC to improve reliability of the IC.

摘要翻译： 集成电路技术领域本发明涉及集成电路。 具体地说，本发明涉及一种包括接收输入信号的接收级的IC，用于产生具有比输入信号更大的电压范围的输出信号的输出级和电平转换器。 本发明的实施例提供了一种用于制造IC的结构和方法，其中电平移位器被并入IC内以提高IC的可靠性。