公开(公告)号：US20090315115A1

公开(公告)日：2009-12-24

申请号：US12214854

申请日：2008-06-23

Applicant: Beichao Zhang ,  Johnny Widodo ,  Juan Boon Tan ,  Yong Kong Siew ,  Fan Zhang ,  Haifeng Sheng ,  Wenhe Lin ,  Young Way Teh ,  Jinping Liu ,  Vincent Ho ,  Liang Choo Hsia

Inventor： Beichao Zhang ,  Johnny Widodo ,  Juan Boon Tan ,  Yong Kong Siew ,  Fan Zhang ,  Haifeng Sheng ,  Wenhe Lin ,  Young Way Teh ,  Jinping Liu ,  Vincent Ho ,  Liang Choo Hsia

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L29/7846

Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance.

Abstract translation: 制造半导体器件的方法（和半导体器件）通过在STI区域中注入离子来提供浅沟槽隔离（STI）结构或区域。 在植入之后，区域（衬底材料和不同元素的离子）进行热退火，产生用于隔离两个相邻的场效应晶体管（FET）的电介质材料。 这消除了去除衬底材料以形成沟槽并用电介质材料重新填充沟槽的常规步骤。 将氮离子注入到邻近p型FET的STI区域中，对晶体管沟道区域施加压缩应力以增强晶体管性能。 将氧离子注入到与n型FET相邻的STI区域中，对晶体管沟道区域施加拉伸应力以增强晶体管性能。

公开(公告)号：US20080124880A1

公开(公告)日：2008-05-29

申请号：US11534651

申请日：2006-09-23

Applicant: Wenhe Lin ,  Randy William Mann ,  Padraic C. Shafer ,  Christopher Vincent Baiocco ,  Zhijoing Luo ,  Haining S. Yang ,  Xiangdong Chen

Inventor： Wenhe Lin ,  Randy William Mann ,  Padraic C. Shafer ,  Christopher Vincent Baiocco ,  Zhijoing Luo ,  Haining S. Yang ,  Xiangdong Chen

IPC: H01L21/336

CPC classification number: H01L29/6659 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

Abstract: Some non-limiting example embodiments comprise a disposable spacer formation and removal process and a stress capping layer process. We provide a gate structure over a substrate. We form disposable spacers abutting the at least one gate sidewall. We form S/D regions adjacent the disposable spacers. We remove the disposable spacers. We can form silicide regions over the S/D and gate. In an aspect, we can deposit a stress inducing layer over the gate and surface portions of the substrate adjacent to the gate, wherein the stress inducing liner provides a stress to a portion of the substrate underlying the gate electrode.

Abstract translation: 一些非限制性示例性实施例包括一次性间隔物形成和移除过程以及应力覆盖层过程。 我们在衬底上提供栅极结构。 我们形成邻接至少一个栅极侧壁的一次性间隔物。 我们在一次性间隔物附近形成S / D区域。 我们取出一次性垫片。 我们可以在S / D和门上形成硅化物区域。 在一方面，我们可以在邻近栅极的基板的栅极和表面部分上沉积应力诱导层，其中应力诱导衬垫向栅电极下方的衬底的一部分提供应力。

公开(公告)号：US20070161244A1

公开(公告)日：2007-07-12

申请号：US11164417

申请日：2005-11-22

Applicant: Brian J. Greene ,  Chung Woh Lai ,  Yong Meng Lee ,  Wenhe Lin ,  Siddhartha Panda ,  Kern Rim ,  Young Way Teh

Inventor： Brian J. Greene ,  Chung Woh Lai ,  Yong Meng Lee ,  Wenhe Lin ,  Siddhartha Panda ,  Kern Rim ,  Young Way Teh

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/31116 ,  H01L21/31144 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.

Abstract translation: 后硅化物间隔物去除的方法（和装置）包括通过使用氧化物层和氮化物层中的至少一种来防止对硅化物间隔物的损害。

公开(公告)号：US20060249794A1

公开(公告)日：2006-11-09

申请号：US11122666

申请日：2005-05-04

Applicant: Young Teh ,  Yong Lee ,  Chung Lai ,  Wenhe Lin ,  Khee Lim ,  Wee Tan ,  John Sudijono ,  Hui Koh ,  Liang Hsia

Inventor： Young Teh ,  Yong Lee ,  Chung Lai ,  Wenhe Lin ,  Khee Lim ,  Wee Tan ,  John Sudijono ,  Hui Koh ,  Liang Hsia

IPC: H01L29/772 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823864

Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

Abstract translation: 从NMOS晶体管的栅极去除间隔物的示例性过程。 在NMOS和PMOS晶体管和衬底上形成应力产生层。 在一个实施例中，栅极上的间隔物被去除，使得应力层更靠近器件的通道。 应力产生层优选为拉伸氮化物层。 应力产生层优选为接触蚀刻停止衬层。 在一个实施例中，栅极，源极和漏极区域在形成应力产生层之前具有硅化物层。 该实施例改善了NMOS晶体管的性能。

公开(公告)号：US07005716B2

公开(公告)日：2006-02-28

申请号：US10853454

申请日：2004-05-25

Applicant: Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

Inventor： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66545 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/517

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.

公开(公告)号：US06750519B2

公开(公告)日：2004-06-15

申请号：US10266714

申请日：2002-10-08

Applicant: Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

Inventor： Wenhe Lin ,  Mei-Sheng Zhou ,  Kin Leong Pey ,  Simon Chooi

IPC: H01L2976

CPC classification number: H01L29/66545 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/517

Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.

Abstract translation: 描述形成双金属栅极CMOS晶体管的方法。 半导体衬底的NMOS和PMOS有源区由隔离区隔开。 金属层沉积在每个有源区域中的栅极电介质层上。 将硅离子注入到一个有源区域中的金属层中以形成硅化物以形成金属硅化物层的注入金属层。 此后，金属层和金属硅化物层被图案化以在一个有源区域中形成金属栅极，在另一个有源区域中形成金属硅化物栅极，其中具有较高功函数的栅极的有源区是PMOS有源区。 或者，两个栅极可以是金属硅化物栅极，其中两个栅极的硅浓度不同。 或者，可以在每个有源区域中形成伪栅极并且被电介质层覆盖。 介电层被平坦化，从而暴露虚拟栅极。 去除虚拟栅极留下栅极开口到半导体衬底。 金属层沉积在栅极开口内的栅极电介质层上，形成金属栅极。 一个或两个栅极是硅植入和硅化的。 PMOS栅极具有较高的功函数。

公开(公告)号：US06664156B1

公开(公告)日：2003-12-16

申请号：US10209573

申请日：2002-07-31

Applicant: Chew Hoe Ang ,  Eng Hua Lim ,  Wenhe Lin ,  Jia Zhen Zheng

Inventor： Chew Hoe Ang ,  Eng Hua Lim ,  Wenhe Lin ,  Jia Zhen Zheng

IPC: H01L21311

CPC classification number: H01L29/6653 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method of fabrication of L-shaped spacers in a semiconductor device. A gate structure is provided over a substrate. We form a first dielectric layer over the gate dielectric layer and the substrate. Next, a second dielectric layer is formed over the first dielectric layer. Then, we form a third dielectric layer over the second dielectric layer. The third dielectric layer is anisotropically etched to form a disposable spacer on the second dielectric layer. The second dielectric layer and the first dielectric layer are anisotropically etched using the disposable spacer as a mask to form a top and a bottom L-shaped spacer. The disposable spacer is removed. In preferred embodiments, the first, second and third dielectric layers are formed by atomic layer deposition (ALD) or ALCVD processes.

Abstract translation: 一种在半导体器件中制造L形间隔物的方法。 栅极结构设置在衬底上。 我们在栅极电介质层和衬底上形成第一电介质层。 接下来，在第一电介质层上形成第二电介质层。 然后，在第二电介质层上形成第三电介质层。 第三介电层被各向异性蚀刻以在第二介电层上形成一次性间隔物。 使用一次性间隔件作为掩模对第二介电层和第一介电层进行各向异性蚀刻，以形成顶部和底部的L形间隔件。 去除一次性间隔物。 在优选实施例中，第一，第二和第三电介质层通过原子层沉积（ALD）或ALCVD工艺形成。

公开(公告)号：US08624329B2

公开(公告)日：2014-01-07

申请号：US12613541

申请日：2009-11-06

Applicant: Yong Meng Lee ,  Young Way Teh ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  Hui Peng Koh ,  John Sudijono ,  Liang Choo Hsia

Inventor： Yong Meng Lee ,  Young Way Teh ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  Hui Peng Koh ,  John Sudijono ,  Liang Choo Hsia

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/823864 ,  H01L21/823871 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Abstract translation: 第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。 第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。 这用于减小寄生电容。 此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。 示例性实施例可以提高设备性能，例如边缘振荡器的性能。

公开(公告)号：US20100059831A1

公开(公告)日：2010-03-11

申请号：US12613541

申请日：2009-11-06

Applicant: Yong Meng Lee ,  Young Way Teh ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  Hui Peng Koh ,  John Sudijono ,  Liang Choo Hsia

Inventor： Yong Meng Lee ,  Young Way Teh ,  Chung Woh Lai ,  Wenhe Lin ,  Khee Yong Lim ,  Wee Leng Tan ,  Hui Peng Koh ,  John Sudijono ,  Liang Choo Hsia

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/31 ,  H01L21/306

CPC classification number: H01L21/823864 ,  H01L21/823871 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Abstract translation: 第一示例性实施例提供了从栅极去除第一间隔物并将低k材料并入到ILD层中以提高器件性能的方法。 第二示例性实施例包括用低k间隔物硅化后替换第一间隔物。 这用于减小寄生电容。 此外，通过仅在硅化后实现低k间隔物，实施方案的低k间隔物不受多次高剂量离子注入和抗蚀剂剥离步骤的影响。 示例性实施例可以提高设备性能，例如边缘振荡器的性能。

公开(公告)号：US07615433B2

公开(公告)日：2009-11-10

申请号：US11304455

申请日：2005-12-15

Applicant: Khee Yong Lim ,  Victor Chan ,  Eng Hua Lim ,  Wenhe Lin ,  Jamin F. Fen

Inventor： Khee Yong Lim ,  Victor Chan ,  Eng Hua Lim ,  Wenhe Lin ,  Jamin F. Fen

IPC: H01L21/336 ,  H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/3003 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823864 ,  H01L29/7843

Abstract: A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.

Abstract translation: 使用PFET压缩蚀刻停止衬垫和NFET拉伸蚀刻停止衬垫以及在含氘气氛中的两个退火来形成具有PFET和NFET晶体管的器件的方法。 该方法包括：在PFET区域中的NFET区域中提供NFET晶体管和PFET晶体管。 我们在NFET区域上形成NFET拉伸接触蚀刻停止衬垫。 然后我们进行第一次氘退火。 我们在PFET区域上形成PFET压电蚀刻停止衬垫。 我们在衬底上形成具有接触开口的（ILD）电介质层。 我们进行第二次氘退火。 第二次氘退火的温度小于第一次氘退火的温度。