公开(公告)号：US20100038991A1

公开(公告)日：2010-02-18

申请号：US12232033

申请日：2008-09-10

Applicant: Wen-Ching Shih ,  Hui-Min Wang

Inventor： Wen-Ching Shih ,  Hui-Min Wang

IPC: H01L41/04

CPC classification number: H03H3/10 ,  H03H9/02574

Abstract: A high frequency SAW device and the substrate thereof are disclosed. The disclosed high frequency SAW device does not need to use the conventional and expensive sapphire substrate as its substrate. Besides, the disclosed substrate for a high-frequency SAW device can replace the conventional sapphire substrate in the use of the substrate for a high frequency SAW device. The disclosed high frequency SAW device comprises: a substrate; a first buffering layer forming on the surface of the substrate; a second buffering layer forming on the surface of the first buffering layer; a piezoelectric layer forming on the surface of the second buffering layer; an input transformation unit; and an output transformation unit, wherein the input transformation unit and the output transformation unit are formed in pairs on the surface of or beneath the piezoelectric layer.

公开(公告)号：US20090092211A1

公开(公告)日：2009-04-09

申请号：US11905797

申请日：2007-10-04

Applicant: Hui-Min Wang

Inventor： Hui-Min Wang

IPC: H04L7/00

CPC classification number: H04L7/0331 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0041

Abstract: A method for adjusting a serial data signal having multiple sets of bits includes the following steps. First, one set of bits in the serial data signal is over-sampled to generate a first set of over-sampled bits. Next, every adjacent two bits of the first set of over-sampled bits are compared to generate one set of edge bits. Then, a delay operation is determined according to the set of edge bits. Afterwards, a displacement operation is executed on next sets of bits in the serial data signal according to the delay operation.

Abstract translation: 一种用于调整具有多组位数的串行数据信号的方法包括以下步骤。 首先，串行数据信号中的一组位被过采样以产生第一组过采样位。 接下来，比较第一组过采样比特的每个相邻的两比特以产生一组边缘比特。 然后，根据边缘位的集合来确定延迟操作。 然后，根据延迟动作对串行数据信号中的下一组位执行位移动作。

公开(公告)号：US20080109787A1

公开(公告)日：2008-05-08

申请号：US11936089

申请日：2007-11-07

Applicant: Hui-Min Wang ,  Hung-Lin Chou ,  Chia-Ching Lin

Inventor： Hui-Min Wang ,  Hung-Lin Chou ,  Chia-Ching Lin

IPC: G06F9/44

CPC classification number: G06F8/33

Abstract: A function reference method of a development tool and a system thereof are disclosed. According to the function reference method, new function database and classified data are described with a text file or a database format file. After the file is read by an add-in module of the development tool, the desired function or object can be loaded into the editing workspace of the development tool through a hierarchical menu or by detecting an input string. Therefore, users can quickly searching and loading new functions.

Abstract translation: 公开了一种开发工具及其系统的功能参考方法。 根据功能参考方法，使用文本文件或数据库格式文件描述新功能数据库和分类数据。 在通过开发工具的附加模块读取文件之后，期望的功能或对象可以通过分层菜单或通过检测输入字符串被加载到开发工具的编辑工作空间中。 因此，用户可以快速搜索和加载新功能。

公开(公告)号：US20070210846A1

公开(公告)日：2007-09-13

申请号：US11371927

申请日：2006-03-10

Applicant: Hui-Min Wang

Inventor： Hui-Min Wang

IPC: H03H11/26

CPC classification number: H03K5/135 ,  H03K2005/00078

Abstract: The present invention provides a digital circuit comprising an inverter gate delay line and a delay adjustment circuit. The inverter gate delay line comprises a series of a plurality of inverter gates that receives a serial data. The delay adjustment circuit comprises a replica inverter gate delay line comprising a series of a plurality of inverter gates and being configured to receive a first signal, a plurality of flip flops, each one of the plurality of flip flops electrically connected to the corresponding inverter gates of the replica inverter gate delay line, wherein the plurality of flip flops store binary information and the first flip flop of the plurality of flip flops receives a second signal which has a time delay with respect to the first signal, an encoder being electrically connected to the plurality of flip flops and determining the numbers of the needed inverter gates of the inverter gate delay line based on the binary information stored in the plurality of flip flops, and a delay selector being electrically connected to the encoder and the plurality of inverter gates of the inverter gate delay line and causing the serial data delayed by the inverter gates of the inverter gate delay line, wherein the numbers of the inverter gates of the inverter gate delay line are determined by an output of the encoder.

Abstract translation: 本发明提供一种数字电路，包括反相门延迟线和延迟调整电路。 逆变器门延迟线包括一系列接收串行数据的反相器门。 延迟调整电路包括复制反相器门延迟线，其包括一系列多个反相器门，并且被配置为接收第一信号，多个触发器，多个触发器中的每一个电连接到相应的反相器门 其中所述多个触发器存储二进制信息，并且所述多个触发器中的第一触发器接收相对于所述第一信号具有时间延迟的第二信号，编码器电连接到 多个触发器，并且基于存储在多个触发器中的二进制信息确定反相器门延迟线所需的反相器门的数量;以及延迟选择器，电连接到编码器和多个反相器门 逆变器门延迟线并使逆变器门延迟线延迟的串行数据延迟，其中 逆变器门延迟线的反相器门数由编码器的输出决定。

公开(公告)号：US20060239383A1

公开(公告)日：2006-10-26

申请号：US11160526

申请日：2005-06-28

Applicant: Hui-Min Wang ,  Chung-Ming Huang ,  Lin-Kai Bu

Inventor： Hui-Min Wang ,  Chung-Ming Huang ,  Lin-Kai Bu

IPC: H04L27/00 ,  H04L7/02

CPC classification number: H04L5/023 ,  H04L7/0008 ,  H04L7/033

Abstract: A multi-channel receiver, digital edge tuning circuit and a method for operating the same is disclosed. The digital edge tuning circuit for tuning phases of an input signal and a clock signal, comprises a delay-tuning circuit for receiving the input signal and delaying the input signal to generate a fine-tuned signal; a delay set comprising a plurality of delays connected serially one by one, the input of the delay set coupled to the fine-tune circuit, for receiving the fine-tuned signal; a plurality of sample/hold circuits, each of the sample/hold circuits coupled to a corresponding output of one of the delays and the fine-tune circuit, for sampling and holding the corresponding output; and a dynamic edge tuning circuit, coupled to the sample/hold circuits, for controlling a common delay time delayed by the delay-tuning circuit according to which one of the sample/hold circuits samples a data edge of the input signal.

Abstract translation: 公开了一种多通道接收机，数字边缘调谐电路及其操作方法。 用于调谐输入信号和时钟信号的相位的数字边沿调谐电路包括延迟调谐电路，用于接收输入信号并延迟输入信号以产生微调信号; 延迟集合，包括串联地逐个连接的多个延迟，耦合到微调电路的延迟集合的输入，用于接收微调信号; 多个采样/保持电路，每个采样/保持电路耦合到延迟中的一个的对应输出和微调电路，用于采样和保持相应的输出; 以及耦合到采样/保持电路的动态边沿调谐电路，用于根据哪个采样/保持电路对输入信号的数据沿进行采样来控制由延迟调谐电路延迟的公共延迟时间。