公开(公告)号：US20160202975A1

公开(公告)日：2016-07-14

申请号：US15077093

申请日：2016-03-22

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  Erdinc Ozturk ,  James D. Guilford ,  Gilbert M. Wolrich

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/34 ,  G06F9/3887

Abstract: According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction having a first operand, a second operand, a third operand, and a fourth operand. The first operand is to specify a first storage location to store an accumulated value; the second operand is to specify a second storage location to store a first value and a second value; and the third operand is to specify a third storage location to store a third value. The processor further includes an execution unit coupled to the instruction decoder to perform the multiply-accumulate operation to multiply the first value with the second value to generate a multiply result and to accumulate the multiply result and at least a portion of a third value to an accumulated value based on the fourth operand.

Abstract translation: 根据一个实施例，处理器包括指令解码器，用于接收处理多重累积运算的指令，该指令具有第一操作数，第二操作数，第三操作数和第四操作数。 第一个操作数是指定一个存储累积值的第一个存储位置; 第二操作数是指定存储第一值和第二值的第二存储位置; 并且第三操作数是指定存储第三值的第三存储位置。 所述处理器还包括执行单元，其耦合到所述指令解码器以执行所述乘法运算，以将所述第一值乘以所述第二值以产生乘法结果，并将乘法结果和第三值的至少一部分累积到 基于第四操作数的累计值。

公开(公告)号：US20160034282A1

公开(公告)日：2016-02-04

申请号：US14880166

申请日：2015-10-09

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80

CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G06F15/8007 ,  G06F21/602 ,  G06F21/64

Abstract: Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.

Abstract translation: 说明和逻辑提供SIMD安全散列圆切片功能。 一些实施例包括处理器，包括：解码级，用于解码用于SIMD安全散列算法圆切片的指令，指定源数据操作数集合的指令，消息加常数操作数集合，安全散列的圆切片部分 圆周运算，旋转设定部分旋转设定。 处理器执行单元响应于解码的指令，在源数据操作数集合上执行循环迭代的安全散列圆切片集合，应用消息加常数操作数集合和旋转器集合，并且存储 SIMD目的寄存器中的指令。 该指令的一个实施例将哈希循环类型指定为四个MD5循环类型之一。 其他实施例可以通过立即操作数来指定散列循环类型，作为三种SHA-1轮型之一或SHA-2轮型。

公开(公告)号：US09027104B2

公开(公告)日：2015-05-05

申请号：US13843141

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford

IPC: G06F21/72 ,  H04L9/06

CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F21/602 ,  G06F21/64 ,  G06F21/72

Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.

Abstract translation: 方面的方法包括接收指令。 该指令指示包括安全散列算法2（SHA2）散列算法的当前轮（i）的状态数据元素ai，bi，ei和fi的第一打包数据的第一来源。 该指令指示第二打包数据的第二来源。 第一打包数据具有小于SHA2散列算法的八个状态数据元素ai，bi，ci，di，ei，fi，gi，hi的组合宽度的比特宽度。 该方法还包括响应于指令将结果存储在由指令指示的目的地中。 结果包括已经通过至少一轮的SHA2散列算法从相应的状态数据元素ai，bi，ei和fi更新的更新的状态数据元素ai +，bi +，ei +和fi +。

公开(公告)号：US20150089195A1

公开(公告)日：2015-03-26

申请号：US14556931

申请日：2014-12-01

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Erdinc Ozturk ,  Wajdi K. Feghali ,  Gilbert M. Wolrich ,  Martin G. Dixon

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3893

Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

Abstract translation: 执行换档和异或运算的方法和装置。 在一个实施例中，一种装置包括执行第一指令的执行资源。 响应于第一指令，所述执行资源对至少一个值执行移位和异或。

公开(公告)号：US08924741B2

公开(公告)日：2014-12-30

申请号：US13731004

申请日：2012-12-29

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap

IPC: H04L29/06 ,  G06F21/60

CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3887 ,  G06F15/8007 ,  G06F21/602 ,  G06F21/64

Abstract: Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.

Abstract translation: 说明和逻辑提供SIMD安全散列圆切片功能。 一些实施例包括处理器，包括：解码级，用于解码用于SIMD安全散列算法圆切片的指令，指定源数据操作数集合的指令，消息加常数操作数集合，安全散列的圆切片部分 圆周运算，旋转设定部分旋转设定。 处理器执行单元响应于解码的指令，在源数据操作数集合上执行循环迭代的安全散列圆切片集合，应用消息加常数操作数集合和旋转器集合，并且存储 SIMD目的寄存器中的指令。 该指令的一个实施例将哈希循环类型指定为四个MD5循环类型之一。 其他实施例可以通过立即操作数来指定散列循环类型，作为三种SHA-1轮型之一或SHA-2轮型。

公开(公告)号：US20140122839A1

公开(公告)日：2014-05-01

申请号：US13997186

申请日：2011-12-22

Applicant: INTEL CORPORATION

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Sean M. Gulley ,  Martin G. Dixon

IPC: G06F9/30

CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

Abstract translation: 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下所述。 a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四进制字的第一输入和用于接收第二四字的第二输入; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

公开(公告)号：US11900108B2

公开(公告)日：2024-02-13

申请号：US17461949

申请日：2021-08-30

Applicant: Intel Corporation

Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30094 ,  G06F9/30098

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

公开(公告)号：US20210036848A1

公开(公告)日：2021-02-04

申请号：US16928558

申请日：2020-07-14

Applicant: Intel Corporation

Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  G06F9/38

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

公开(公告)号：US10778425B2

公开(公告)日：2020-09-15

申请号：US16223109

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Sean M. Gulley ,  Gilbert M. Wolrich ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: H04L9/08 ,  H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  G06F9/38

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

公开(公告)号：US10581594B2

公开(公告)日：2020-03-03

申请号：US16017519

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford

IPC: H04L9/06 ,  G06F21/64 ,  G06F9/30 ,  G06F21/72 ,  G06F21/60

Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.