公开(公告)号：US20230057384A1

公开(公告)日：2023-02-23

申请号：US17408157

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Brandon C. MARIN ,  Hiroki TANAKA ,  Jason M. GAMBA ,  Srinivas V. PIETAMBARAM

IPC: H01L21/683 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments disclosed herein include carriers and methods of using the carriers to assemble electronic packages. In an embodiment, a carrier for electronic packaging assembly comprises a mold layer with a first surface and a second surface. In an embodiment, a plurality of glass substrates are embedded in the mold layer. In an embodiment, individual ones of the glass substrates comprise a third surface and a fourth surface, where the third surface of the glass substrate is substantially coplanar with the first surface of the mold layer.

公开(公告)号：US20230015619A1

公开(公告)日：2023-01-19

申请号：US17952080

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Kristof DARMAWAIKARTA ,  Robert MAY ,  Sashi KANDANUR ,  Sri Ranga Sai BOYAPATI ,  Srinivas PIETAMBARAM ,  Steve CHO ,  Jung Kyu HAN ,  Thomas HEATON ,  Ali LEHAF ,  Ravindranadh ELURI ,  Hiroki TANAKA ,  Aleksandar ALEKSOV ,  Dilan SENEVIRATNE

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768

Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

公开(公告)号：US20220187548A1

公开(公告)日：2022-06-16

申请号：US17122340

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Divya PRATAP ,  Hiroki TANAKA ,  Nitin DESHPANDE ,  Omkar KARHADE ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI ,  Srinivas V. PIETAMBARAM ,  Xiaoqian LI ,  Sai VADLAMANI ,  Jeremy ECTON

IPC: G02B6/42 ,  G02F1/01 ,  G02F1/09

Abstract: Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

公开(公告)号：US20210035901A1

公开(公告)日：2021-02-04

申请号：US17075533

申请日：2020-10-20

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Jung Kyu HAN ,  Ali LEHAF ,  Steve CHO ,  Thomas HEATON ,  Hiroki TANAKA ,  Kristof DARMAWIKARTA ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

Abstract: A package assembly includes a substrate and at least a first die having a first contact array and a second contact array. First and second via assemblies are respectively coupled with the first and second contact arrays. Each of the first and second via assemblies includes a base pad, a cap assembly, and a via therebetween. One or more of the cap assembly or the via includes an electromigration resistant material to isolate each of the base pad and the cap assembly. Each first cap assembly and via of the first via assemblies has a first assembly profile less than a second assembly profile of each second cap assembly and via of the second via assemblies. The first and second cap assemblies have a common applied thickness in an application configuration. The first and second cap assemblies have a thickness variation of ten microns or less in a reflowed configuration.

公开(公告)号：US20200266184A1

公开(公告)日：2020-08-20

申请号：US16649923

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Robert Alan MAY ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Rahul N. MANEPALLI ,  Sri Ranga Sai BOYAPATI

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065

Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.