公开(公告)号：US20240071883A1

公开(公告)日：2024-02-29

申请号：US17893893

申请日：2022-08-23

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Sashi S. KANDANUR ,  Suddhasattwa NAD ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Jeremy D. ECTON

IPC: H01L23/498 ,  H01L23/15 ,  H01L23/544

CPC classification number: H01L23/49827 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include cores for package substrates. In an embodiment, the core comprises a first substrate, where the first substrate comprises glass. In an embodiment, the core further comprises a first through glass via (TGV) through the first substrate and a second substrate, where the second substrate comprises glass. In an embodiment, the core further comprises a second TGV through the second substrate, where the first TGV is aligned with the second TGV.

公开(公告)号：US20240055345A1

公开(公告)日：2024-02-15

申请号：US17886278

申请日：2022-08-11

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Rahul N. MANEPALLI

IPC: H01L23/522 ,  H01L49/02 ,  H01G11/70 ,  H01L23/15

CPC classification number: H01L23/5223 ,  H01L28/40 ,  H01G11/70 ,  H01L23/15

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a pillar is over the substrate, and a capacitor is over the pillar. In an embodiment, the capacitor comprises a first conductive layer on the pillar, a dielectric layer over the first conductive layer, and a second conductive layer over the dielectric layer.

公开(公告)号：US20230341623A1

公开(公告)日：2023-10-26

申请号：US17729974

申请日：2022-04-26

Applicant: Intel Corporation

Inventor： Brandon C. MARIN

IPC: G02B6/12 ,  G02B6/122

CPC classification number: G02B6/1225 ,  G02B6/12002 ,  G02B2006/12121 ,  G02B2006/1213

Abstract: Embodiments disclosed herein include optical interconnects and methods of forming such optical interconnects. In an embodiment, the optical interconnect comprises a package substrate, where an optical waveguide is embedded in the package substrate. In an embodiment, a photonics integrated circuit (PIC) is over the package substrate, where the PIC comprises a laser that is configured to be optically coupled to the optical waveguide. In an embodiment, the optical interconnect further comprises a plasmonic junction between the laser and the optical waveguide.

公开(公告)号：US20230093258A1

公开(公告)日：2023-03-23

申请号：US17482830

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Haobo CHEN ,  Leonel ARANA

IPC: H01L23/498 ,  H01L23/15 ,  H01L21/48

Abstract: Embodiments include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first substrate, and a second substrate coupled to the first substrate. In an embodiment, the second substrate comprises a core, and the core comprises an organic material. In an embodiment, a third substrate is coupled to the second substrate, and the third substrate comprises a glass layer.

公开(公告)号：US20180033707A1

公开(公告)日：2018-02-01

申请号：US15549970

申请日：2015-03-09

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Trina GHOSH DASTIDAR ,  Dilan SENEVIRATNE ,  Yonggang LI ,  Sirisha CHAVA

IPC: H01L23/14 ,  H05K3/10 ,  H05K3/18 ,  H05K3/06

CPC classification number: H01L23/14 ,  H01L21/4846 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49866 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K3/062 ,  H05K3/105 ,  H05K3/107 ,  H05K3/182 ,  H05K3/185 ,  H05K2201/0209 ,  H05K2203/107

Abstract: Embodiments of the present disclosure describe selective metallization of an integrated circuit (IC) substrate. In one embodiment, an integrated circuit (IC) substrate may include a dielectric material and metal crystals having a polyhedral shape dispersed in the dielectric material and bonded with a ligand that is to ablate when exposed to laser light such that the metal crystals having the ablated ligand are activated to provide a catalyst for selective electroless deposition of a metal. Other embodiments may be described and/or claimed

公开(公告)号：US20240339381A1

公开(公告)日：2024-10-10

申请号：US18130582

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Hiroki TANAKA ,  Veronica STRONG ,  Henning BRAUNISCH ,  Haobo CHEN ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Brandon C. MARIN

IPC: H01L23/482 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/4821 ,  H01L21/76831 ,  H01L23/49827 ,  H01L23/49866 ,  H01L21/30604 ,  H05K2201/09218

Abstract: Embodiments disclosed herein include an interposer. In an embodiment, the interposer comprises a substrate, where the substrate comprises a glass layer. In an embodiment, a trace is on the substrate, where the trace has a bottom surface, sidewall surfaces, and a top surface. In an embodiment, the sidewall surfaces and the top surface are exposed to air. In an embodiment, a trench into the substrate is adjacent to at least one sidewall surface of the trace.

公开(公告)号：US20240332195A1

公开(公告)日：2024-10-03

申请号：US18129879

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Naiya SOETAN-DODD ,  Srinivas V. PIETAMBARAM ,  Suddhasattwa NAD ,  Brandon C. MARIN ,  Sheng C. LI ,  Liwei CHENG

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16235

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a core, where the core comprises glass. In an embodiment, a cavity is in the core, and a bridge is in the cavity. In an embodiment, the bridge comprises through substrate vias (TSVs). In an embodiment, pads are at a bottom of the cavity, where the TSVs are electrically coupled to the pads.

公开(公告)号：US20240071935A1

公开(公告)日：2024-02-29

申请号：US17895965

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08225 ,  H01L2224/80894 ,  H01L2224/80895

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate, where the first substrate comprises glass, and a second substrate over the first substrate, where the second substrate comprises glass. In an embodiment, electrically conductive routing is provided in the second substrate. In an embodiment, a first die is over the second substrate, and a second die is over the second substrate. In an embodiment, the electrically conductive routing electrically couples the first die to the second die.

公开(公告)号：US20240071848A1

公开(公告)日：2024-02-29

申请号：US17895916

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Bai NIE ,  Gang DUAN ,  Kyle ARRINGTON ,  Ziyin LIN ,  Hongxia FENG ,  Yiqun BAI ,  Xiaoying GUO ,  Dingying David XU ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.

公开(公告)号：US20240063203A1

公开(公告)日：2024-02-22

申请号：US17889962

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Navneet SINGH ,  Sushil PADMANABHAN ,  Samarth ALVA

IPC: H01L25/18 ,  H01L23/15 ,  H01L23/538 ,  H01L23/48 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/481 ,  H01L23/5384 ,  H01L21/486 ,  H01L21/4857 ,  H01L25/50 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass, and buildup layers over the first substrate. In an embodiment, a first die is over the buildup layers, a second die is over the buildup layers and adjacent to the first die, and where conductive routing in the buildup layers electrically couples the first die to the second die.