公开(公告)号：US20240429173A1

公开(公告)日：2024-12-26

申请号：US18823186

申请日：2024-09-03

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Chia-Pin CHIU ,  Aleksandar ALEKSOV ,  Hinmeng AU ,  Stefanie M. LOTZ ,  Johanna M. SWAN ,  Sujit SHARAN

IPC: H01L23/538 ,  H01L21/683 ,  H01L23/00 ,  H01L23/13 ,  H01L25/065

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20240014149A1

公开(公告)日：2024-01-11

申请号：US18372533

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Thomas SOUNART ,  Kristof DARMAWIKARTA ,  Henning BRAUNISCH ,  Prithwish CHATTERJEE ,  Andrew J. BROWN

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/642 ,  H01L23/49894 ,  H01L23/49838 ,  H01L24/16 ,  H01L23/49827 ,  H01L21/4846 ,  H01L2224/16265 ,  H01L2224/16225 ,  H01L2924/19103 ,  H01L2924/19041

Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

公开(公告)号：US20230027030A1

公开(公告)日：2023-01-26

申请号：US17958296

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Changhua LIU ,  Xiaoying GUO ,  Aleksandar ALEKSOV ,  Steve S. CHO ,  Leonel ARANA ,  Robert MAY ,  Gang DUAN

IPC: H01L23/00

Abstract: A patch structure of an integrated circuit package comprises a core having a first side facing downwards and a second side facing upwards. A first solder resist (SR) layer is formed on the first side of the core, wherein the first SR layer comprises a first layer interconnect (FLI) and has a first set of one or more microbumps thereon to bond to one or more logic die. A second solder resist (SR) layer is formed on the second side of the core, wherein the second SR layer has a second set of one or more microbumps thereon to bond with a substrate. One or more bridge dies includes a respective sets of bumps, wherein the one or more bridge dies is disposed flipped over within the core such that the respective sets of bumps face downward and connect to the first set of one or more microbumps in the FLI.

公开(公告)号：US20220407202A1

公开(公告)日：2022-12-22

申请号：US17350791

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Neelam PRABHU GAUNKAR ,  Georgios C. DOGIAMIS ,  Veronica STRONG ,  Aleksandar ALEKSOV

IPC: H01P3/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/66

Abstract: Embodiments disclosed herein include coplanar waveguides and methods of forming coplanar waveguides. In an embodiment, a coplanar waveguide comprises a core, and a signal trace on the core. In an embodiment, the signal trace has a first edge and a second edge. In an embodiment, a first ground trace is over the core, and the first ground trace is adjacent to the first edge of the signal trace. In an embodiment, a first ground via plane is below the first ground trace. The coplanar waveguide may further comprise a second ground trace over the core, and the second ground trace is adjacent to the second edge of the signal trace. In an embodiment, a second ground via plane below the second ground trace.

公开(公告)号：US20220406696A1

公开(公告)日：2022-12-22

申请号：US17349697

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Telesphor KAMGAING ,  Veronica STRONG ,  Georgios C. DOGIAMIS ,  Neelam PRABHU GAUNKAR

IPC: H01L23/498 ,  H01L23/15 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment the package substrate comprises a core and buildup layers on the core. In an embodiment, first level interconnect (FLI) pads are on a topmost buildup layer, and the FLI pads have a pitch. In an embodiment, a plurality of vertically oriented planes are embedded in the core, and the vertically oriented planes are spaced at the pitch.

公开(公告)号：US20220254754A1

公开(公告)日：2022-08-11

申请号：US17728813

申请日：2022-04-25

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20210134726A1

公开(公告)日：2021-05-06

申请号：US17144130

申请日：2021-01-07

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Chia-Pin CHIU ,  Aleksandar ALEKSOV ,  Hinmeng AU ,  Stefanie M. LOTZ ,  Johanna M. SWAN ,  Sujit SHARAN

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20200075491A1

公开(公告)日：2020-03-05

申请号：US16611841

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Feras EID ,  Thomas L. SOUNART ,  Aleksandar ALEKSOV ,  Johanna M. SWAN

IPC: H01L23/538 ,  H01L23/64 ,  H01G7/06 ,  H01L27/01

Abstract: Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a tunable ferroelectric capacitor formed in-situ with at least one organic dielectric layer of the plurality of organic dielectric layers. The tunable ferroelectric capacitor (e.g., varactor) includes first and second conductive electrodes and a ferroelectric layer that is positioned between the first and second conductive electrodes.

公开(公告)号：US20190297975A1

公开(公告)日：2019-10-03

申请号：US16303386

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Sasha N. OSTER ,  Feras EID ,  Shawna M. LIFF ,  Thomas L. SOUNART ,  Johanna M. SWAN ,  Baris BICEN ,  Valluri R. RAO

IPC: A41D27/28 ,  A41D13/00 ,  A41D27/24 ,  A61M35/00 ,  A61M5/145

Abstract: Embodiments of the invention include an active venting system. According to an embodiment of the invention, the active venting system may include a substrate having one or more seams formed through the substrate. In order to open the vents defined by the seams through the substrate, a piezoelectric layer may be formed proximate to one or more of the seams. Additional embodiments may include a first electrode and a second electrode that contact the piezoelectric layer in order to provide a voltage differential across the piezoelectric layer. In an embodiment the active venting system may be integrated into a garment. In such an embodiment, the garment may also include an electronics module for controlling the actuators. Additionally, conductive traces may be printed on the garment or sewn into the garment to provide electrical connections from the electronics module to each of the piezoelectric actuators.

公开(公告)号：US20190169020A1

公开(公告)日：2019-06-06

申请号：US15832223

申请日：2017-12-05

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Robert A. MAY ,  Changhua LIU ,  Hiroki TANAKA ,  Feras EID

IPC: B81B7/02 ,  B81C1/00 ,  H01L23/498

Abstract: A package substrate is provided which comprises: one or more first conductive contacts on a first surface; one or more second conductive contacts on a second surface opposite the first surface; a dielectric layer between the first and the second surfaces; and an embedded sensing or actuating element on the dielectric layer conductively coupled with one of the first conductive contacts, wherein the embedded sensing or actuating element comprises a fixed metal layer in the dielectric layer and a flexible metal layer suspended over the fixed metal layer by one or more metal supports on the dielectric layer. Other embodiments are also disclosed and claimed.