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    TOOLS AND METHODS FOR SURFACE LEVELING
    1.
    发明公开
    TOOLS AND METHODS FOR SURFACE LEVELING 审中-公开

    公开(公告)号：US20240282591A1

    公开(公告)日：2024-08-22

    申请号：US18171683

    申请日：2023-02-21

    Applicant: Intel Corporation

    Inventor： Oladeji FADAYOMI ,  Shaojiang CHEN ,  Jeremy ECTON ,  Matthew TINGEY ,  Srinivas PIETAMBARAM ,  Leonel ARANA

    IPC: H01L21/48 ,  C23F1/02

    CPC classification number: H01L21/486 ,  C23F1/02

    Abstract: The present disclosure is directed to a planarization tool having at least one module with a target holder for supporting a target with a metal layer, at least one of a plurality of etch inhibitor dispensers for discharging an etch inhibitor toward the target, and a plurality of nozzles for discharging a chemical etchant at an angle towards the target to perform selective removal of the metal layer for planarization of the target. In an aspect, the plurality of etch inhibitor dispensers and the plurality of nozzles may be combined as a single unit to discharge the chemical etchant and the etch inhibitor together. In another aspect, the plurality of etch inhibitor dispensers and the plurality of nozzles may be configured in a single module or separate modules.

    HYBRID FINE LINE SPACING ARCHITECTURE FOR BUMP PITCH SCALING
    2.
    发明申请
    HYBRID FINE LINE SPACING ARCHITECTURE FOR BUMP PITCH SCALING 审中-公开

    公开(公告)号：US20200312665A1

    公开(公告)日：2020-10-01

    申请号：US16363688

    申请日：2019-03-25

    Applicant: Intel Corporation

    Inventor： Suddhasattwa NAD ,  Jeremy ECTON ,  Bai NIE ,  Rahul MANEPALLI ,  Marcel WALL

    IPC: H01L21/28 ,  H01L21/48 ,  H01L23/00

    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.

    METHOD FOR FORMING EMBEDDED GROUNDING PLANES ON INTERCONNECT LAYERS
    3.
    发明申请
    METHOD FOR FORMING EMBEDDED GROUNDING PLANES ON INTERCONNECT LAYERS 审中-公开

    公开(公告)号：US20200328131A1

    公开(公告)日：2020-10-15

    申请号：US16380486

    申请日：2019-04-10

    Applicant: Intel Corporation

    Inventor： Brandon C. MARIN ,  Kristof DARMAWIKARTA ,  Roy DITTLER ,  Jeremy ECTON ,  Darko GRUJICIC

    IPC: H01L23/31 ,  H01L23/488

    Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

    CAPACITORS WITH NANOISLANDS ON CONDUCTIVE PLATES
    8.
    发明申请
    CAPACITORS WITH NANOISLANDS ON CONDUCTIVE PLATES 有权

    公开(公告)号：US20210066447A1

    公开(公告)日：2021-03-04

    申请号：US16560647

    申请日：2019-09-04

    Applicant: Intel Corporation

    Inventor： Srinivas PIETAMBARAM ,  Brandon C. MARIN ,  Jeremy ECTON ,  Hiroki TANAKA ,  Frank TRUONG

    IPC: H01L49/02 ,  H01G4/008 ,  H01G4/12 ,  H01L21/48 ,  H01G4/28

    Abstract: Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique.

    SANDWICH-MOLDED CORES FOR HIGH-INDUCTANCE ARCHITECTURES
    9.
    发明申请
    SANDWICH-MOLDED CORES FOR HIGH-INDUCTANCE ARCHITECTURES 有权

    公开(公告)号：US20210014972A1

    公开(公告)日：2021-01-14

    申请号：US16505403

    申请日：2019-07-08

    Applicant: Intel Corporation

    Inventor： Brandon C. MARIN ,  Tarek IBRAHIM ,  Srinivas PIETAMBARAM ,  Andrew J. BROWN ,  Gang DUAN ,  Jeremy ECTON ,  Sheng C. LI

    IPC: H05K1/16 ,  H01L23/00 ,  H01F27/40 ,  H05K1/11 ,  H05K3/40 ,  H05K3/28

    Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

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