公开(公告)号：US09501405B2

公开(公告)日：2016-11-22

申请号：US14705195

申请日：2015-05-06

Applicant: Intel Corporation

Inventor： Prashant S. Damle ,  Robert W. Faber ,  Ningde Xie

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7211

Abstract: Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems and methods allow physical addresses of memory cells subjected to a high number of write cycles to be swapped with physical addresses of memory cells subjected to a lower number of write cycles. The physical address of a group of memory cells is a “hot address” if the write cycle count for that memory cell group exceeds a specified threshold. If the write cycle count for a group of memory cells does not exceed the specified threshold, then the physical address of that memory cell group is a “cold address”. The systems and methods allow the specified threshold of write cycle counts to be dynamically incremented to assure that cold addresses are available for swapping with hot addresses in the memory cell address space.

公开(公告)号：US09286975B2

公开(公告)日：2016-03-15

申请号：US14204376

申请日：2014-03-11

Applicant: Intel Corporation

Inventor： Daniel J. Chu ,  Kiran Pangal ,  Nathan R. Franklin ,  Prashant S. Damle ,  Hu Chaohong

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/0061 ,  G11C2013/0047 ,  G11C2013/0052

Abstract: The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.

Abstract translation: 本公开涉及减轻交叉点存储器中的读取干扰。 设备可以包括被配置为选择用于存储器访问操作的目标存储器单元的存储器控​​制器。 存储器控制器包括感测模块，其被配置为确定在感测间隔期间是否发生快照事件; 以及写回模块，被配置为如果检测到快照事件，则将逻辑1写回到所述存储器单元。