公开(公告)号：US20190044732A1

公开(公告)日：2019-02-07

申请号：US15856179

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Andrew Reinders ,  Manoj Sastry ,  Santosh Ghosh ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L29/06 ,  H04L9/30 ,  H04L9/08

Abstract: A technique includes generating a direct anonymous attestation (DAA)-based signature to prove an electronic device is a member of a group. Generating the signature includes determining a reciprocal of a prime modulus, and determining the reciprocal of the prime modulus comprises left bit shifting a Barrett multiplier by a predetermined number of bits and multiplying a result of the left bit shifting of the Barrett multiplier with the prime modulus.

公开(公告)号：US10033534B2

公开(公告)日：2018-07-24

申请号：US14955255

申请日：2015-12-01

Applicant: INTEL CORPORATION

Inventor： Steffen Schulz ,  Rafael Misoczki ,  Manoj R. Sastry ,  Jesse Walker

IPC: H04L9/32 ,  G06F8/65 ,  H04L29/06 ,  H04L9/14 ,  H04L9/30 ,  G06F21/00

Abstract: In a method for validating software updates, a data processing system contains a current version of a software component. The data processing system saves at least first and second current advance keys (AKs). After saving the current AKs, the data processing system receives an update package for a new version of the software component. The data processing system extracts a digital signature and two or more new AKs from the update package. The data processing system uses at least one current AK to determine whether the digital signature is valid. In response to a determination that the digital signature is valid, the data processing system uses a software image from the update package to update the software component, and the data processing system saves the new AKs, for subsequent utilization as the current AKs. Other embodiments are described and claimed.

公开(公告)号：US20180139051A1

公开(公告)日：2018-05-17

申请号：US15351606

申请日：2016-11-15

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj R. Sastry ,  Jesse Walker ,  Li Zhao ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08

CPC classification number: H04L9/3242 ,  H04L9/0637 ,  H04L9/0643

Abstract: Technologies for counter with CBC-MAC (CCM) mode encryption include a computing device that performs a CBC-MAC authentication operation on a message with an encryption key, using a 64-bit block cipher to generate a message authentication code. The computing device generates a first 64-bit authentication block including an 8-bit flag field and a length field of between 11 and 32 bits. The flag field indicates the length of the length field. Performing the CBC-MAC authentication operation includes formatting the message into one or more 64-bit authentication blocks. The computing device performs a counter mode encryption operation on the message with the encryption key using the 64-bit block cipher to generate a cipher text. Performing the counter mode encryption includes generating multiple 64-bit keystream blocks. The computing device generates an authentication tag based on the message authentication code and a first keystream block of keystream blocks. Other embodiments are described and claimed.

公开(公告)号：US11917053B2

公开(公告)日：2024-02-27

申请号：US17707629

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/06 ,  G06F7/503 ,  G06F9/30 ,  H04L9/32

CPC classification number: H04L9/0643 ,  G06F7/503 ,  G06F9/3012 ,  H04L9/3247

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

公开(公告)号：US11777707B2

公开(公告)日：2023-10-03

申请号：US17833498

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew Reinders ,  Rafael Misoczki ,  Rosario Cammarota ,  Manoj Sastry

IPC: H04L9/00 ,  H04L9/06 ,  G06F7/72 ,  G09C1/00 ,  G06F21/72 ,  G06F7/487 ,  G06F21/60 ,  G06N3/063 ,  G06N20/00 ,  G06N3/08

CPC classification number: H04L9/008 ,  G06F7/722 ,  G06N3/08 ,  H04L9/0618

Abstract: Embodiments are directed to homomorphic encryption for machine learning and neural networks using high-throughput Chinese remainder theorem (CRT) evaluation. An embodiment of an apparatus includes a hardware accelerator to receive a ciphertext generated by homomorphic encryption (HE) for evaluation, decompose coefficients of the ciphertext into a set of decomposed coefficients, multiply the decomposed coefficients using a set of smaller modulus determined based on a larger modulus, and convert results of the multiplying back to an original form corresponding to the larger modulus by performing a reverse Chinese remainder theorem (CRT) transform on the results of multiplying the decomposed coefficients.

公开(公告)号：US11751025B2

公开(公告)日：2023-09-05

申请号：US17678265

申请日：2022-02-23

Applicant: Intel Corporation

Inventor： Stefan Fechtel ,  Kilian Roth ,  Bertram Gunzelmann ,  Markus Dominik Mueck ,  Ingolf Karls ,  Zhibin Yu ,  Thorsten Clevorn ,  Nageen Himayat ,  Dave A. Cavalcanti ,  Ana Lucia Pinheiro ,  Bahareh Sadeghi ,  Hassnaa Moustafa ,  Marcio Rogerio Juliato ,  Rafael Misoczki ,  Emily H. Qi ,  Jeffrey R. Foerster ,  Duncan Kitchin ,  Debdeep Chatterjee ,  Jong-Kae Fwu ,  Carlos Aldana ,  Shilpa Talwar ,  Harry G. Skinner ,  Debabani Choudhury

IPC: H04W4/40 ,  H04W4/80 ,  H04W8/08 ,  H04W80/02 ,  H04W80/08

CPC classification number: H04W4/40 ,  H04W4/80 ,  H04W8/08 ,  H04W80/02 ,  H04W80/08

Abstract: A communication device for multi-radio access technology (RAT) communications includes one or more processors and a plurality of transceivers. Each transceiver is configured to operate in at least one RAT of a plurality of RATs. The processors are configured to establish connection with a second communication device using a first transceiver of the plurality of transceivers and a first RAT of the plurality of RATs. A first data stream associated with a communication link connected to the second communication device and a third communication device is receive via a convergence function at the second communication device. The communication link uses a second RAT of the plurality of RATs. A code sequence is applied to a second data stream to generate an encoded second data stream, which is transmitted to the third communication device via a second communication link established based on information received via the first data stream.

公开(公告)号：US11750402B2

公开(公告)日：2023-09-05

申请号：US17534158

申请日：2021-11-23

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/40 ,  H04L9/32 ,  H04L9/06 ,  G06F9/38 ,  H04L9/08 ,  H04L9/00

CPC classification number: H04L9/3247 ,  G06F9/3877 ,  H04L9/0643 ,  H04L9/0861 ,  H04L9/50

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

公开(公告)号：US11722313B2

公开(公告)日：2023-08-08

申请号：US17014600

申请日：2020-09-08

Applicant: Intel Corporation

Inventor： Rafael Misoczki ,  Andrew H. Reinders ,  Santosh Ghosh ,  Manoj Sastry

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14 ,  H04L9/30 ,  G06N10/00

CPC classification number: H04L9/3247 ,  G06N10/00 ,  H04L9/0618 ,  H04L9/0825 ,  H04L9/0852 ,  H04L9/0877 ,  H04L9/14 ,  H04L9/3073 ,  H04L9/0836 ,  H04L9/3239

Abstract: An apparatus comprises a plurality of hardware security modules, at least a first hardware security module in the plurality of hardware security modules comprising processing circuitry to generate a first plurality of pairs of cryptographic key pairs comprising a first plurality of private keys and a first plurality of public keys, forward the first plurality of public keys to a remote computing device, receive, from the remote computing device, a first plurality of ciphertexts, wherein each ciphertext in the plurality of ciphertexts represents an encryption of a cryptographic seed with a public key selected from the plurality of public keys, receive, from a subset of hardware security modules in the plurality of hardware security modules, a subset of private keys.

公开(公告)号：US11362835B2

公开(公告)日：2022-06-14

申请号：US16455978

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Manoj Sastry ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer readable memory; and a signature module to generate a set of cryptographic keys for attestation of group member devices and a set of leaf nodes in a sub-tree of a Merkle tree corresponding to the set of cryptographic keys, forward the set of leaf nodes to a group manager device, receive, from the group manager device, a subset of intermediate nodes in the Merkle tree, the intermediate nodes being common to all available authentications paths through the Merkel tree for signatures originating in the sub-tree, and determine a cryptographic key that defines an authentication path through the Merkle tree, the authentication path comprising one or more nodes from the set of leaf nodes and one or more nodes from the intermediate nodes received from the group manager device. Other examples may be described.

公开(公告)号：US11240039B2

公开(公告)日：2022-02-01

申请号：US16455921

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L29/06 ,  H04L9/32 ,  H04L9/06 ,  G06F9/38 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.