公开(公告)号：US10157672B2

公开(公告)日：2018-12-18

申请号：US15810290

申请日：2017-11-13

Applicant: International Business Machines Corporation

Inventor： David D. Cadigan ,  William V. Huott ,  Adam J. McPadden ,  Anuwat Saetow

IPC: G11C11/412 ,  G11C13/00 ,  G11C14/00 ,  G11C29/12 ,  G11C11/419

Abstract: Embodiments include techniques for static random access memory (SRAM) bitline equalization using phase change material (PCM). The techniques include detecting a defect in SRAM bitlines, and programming a variable resistance PCM cell to offset the detected defect. The techniques also include measuring signal development time for the SRAM bitlines, and adjusting the programming of the variable resistance PCM cell based at least in part on the measured signal development for the SRAM bitlines.

公开(公告)号：US09965346B2

公开(公告)日：2018-05-08

申请号：US15096344

申请日：2016-04-12

Applicant: International Business Machines Corporation

Inventor： David D. Cadigan ,  Charles A. Kilmer ,  Anil B. Lingambudi ,  Adam J. McPadden ,  Anuwat Saetow

IPC: G11C29/00 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/076 ,  G06F11/0727 ,  G06F11/0793 ,  G06F11/1048 ,  G06F11/1076

Abstract: An aspect includes identifying a repaired memory array element in a memory array, and identifying memory array elements in the memory array that are adjacent to the repaired memory array element. A group that includes the repaired and adjacent memory array elements is formed and monitored for error conditions. It is determined whether a number of the error conditions exceeds a threshold. A repair action is performed to the memory array based on determining that the number of error conditions exceeds the threshold.

公开(公告)号：US20170219645A1

公开(公告)日：2017-08-03

申请号：US15008802

申请日：2016-01-28

Applicant: International Business Machines Corporation

Inventor： David D. Cadigan ,  William V. Huott ,  Adam J. McPadden ,  Anuwat Saetow ,  Gary A. Tressler

IPC: G01R31/02

CPC classification number: G01R31/025 ,  G01R31/024 ,  G01R31/2851 ,  G01R31/2856 ,  G01R31/2858 ,  G01R31/3008

Abstract: An integrated circuit is configured to detect current leakage that results from electromigration in the integrated circuit. An isolation power switch selectively connects a target voltage rail in the integrated circuit to a power source. A voltage memory stores a record of an initial voltage decay rate for the target voltage rail while isolated from a manufacturer's power source. A voltage record comparator logic compares the initial voltage decay rate to a field voltage decay rate for the target voltage rail when isolated from a field power source. An output device indicates that a difference between the initial voltage decay rate and the field voltage decay rate for the target voltage rail exceeds a predefined limit, where the difference is a result of current leakage caused by electromigration in the integrated circuit.

公开(公告)号：US09691453B1

公开(公告)日：2017-06-27

申请号：US15044832

申请日：2016-02-16

Applicant: International Business Machines Corporation

Inventor： John S. Bialas, Jr. ,  David D. Cadigan ,  Stephen P. Glancy ,  Warren E. Maule ,  Gary A. Van Huben

IPC: G11C5/14 ,  G11C7/22 ,  G11C7/14

CPC classification number: G11C7/22 ,  G11C5/147 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/2254

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.

公开(公告)号：US20170178703A1

公开(公告)日：2017-06-22

申请号：US15044832

申请日：2016-02-16

Applicant: International Business Machines Corporation

Inventor： John S. Bialas, JR. ,  David D. Cadigan ,  Stephen P. Glancy ,  Warren E. Maule ,  Gary A. Van Huben

IPC: G11C7/22 ,  G11C7/14

CPC classification number: G11C7/22 ,  G11C5/147 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/023 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/2254

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.

公开(公告)号：US09627030B1

公开(公告)日：2017-04-18

申请号：US15044746

申请日：2016-02-16

Applicant: International Business Machines Corporation

Inventor： John S. Bialas, Jr. ,  David D. Cadigan ,  Stephen P. Glancy ,  Warren E. Maule ,  Gary A. Van Huben

IPC: G11C11/4076 ,  G11C11/409

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  G11C29/50012 ,  G11C2029/5004 ,  G11C2207/2254

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

公开(公告)号：US09548773B1

公开(公告)日：2017-01-17

申请号：US15066194

申请日：2016-03-10

Applicant: International Business Machines Corporation

Inventor： David D. Cadigan ,  Samuel R. Connor ,  Michael A. Cracraft ,  William V. Huott ,  Adam J. McPadden ,  Anuwat Saetow ,  Gary A. Tressler

IPC: H04B1/04 ,  H04B17/336

CPC classification number: H04B1/0475 ,  H04B17/17 ,  H04B17/318 ,  H04B17/336

Abstract: A method detects and mitigates harm caused by electromagnetic interference (EMI) to digital transmissions within an electronic circuit. One or more processors check for an initial transmission error during an initial digital transmission between a digital transmitter and a digital receiver on an electronic circuit. In response to detecting the initial transmission error, the processor(s) receive electromagnetic interference (EMI) detection signals from one or more EMI detectors. In response to determining that the EMI detection signals represent an EMI level that exceeds a predetermined value, the processor(s) identify an EMI anomaly source on the electronic circuit and adjusts the EMI anomaly source until the EMI level has been reduced to a nominal level. A copy of the initial digital transmission is then resent from the digital transmitter to the digital receiver. If no transmission error reoccurs, then the EMI anomaly source is kept in the adjusted state.

Abstract translation: 一种方法可以检测和减轻由电磁干扰（EMI）引起的对电子电路内的数字传输的危害。 一个或多个处理器在电子电路上的数字发射机和数字接收机之间的初始数字传输期间检查初始传输错误。 响应于检测到初始传输错误，处理器从一个或多个EMI检测器接收电磁干扰（EMI）检测信号。 响应于确定EMI检测信号表示超过预定值的EMI电平，处理器识别电子电路上的EMI异常源并调整EMI异常源，直到EMI电平降低到标称电平 。 然后，将初始数字传输的副本从数字发射机重新发送到数字接收机。 如果没有发生传输错误，则EMI异常源保持在调整状态。