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公开(公告)号：US11698842B2
公开(公告)日：2023-07-11
申请号：US17496399
申请日：2021-10-07
CPC分类号： G06F11/1666 , G06F11/1068 , G11C29/42 , G11C29/44 , G11C29/52 , G11C29/70 , G11C29/76 , G11C2029/1204
摘要： A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.
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公开(公告)号：US11645171B2
公开(公告)日：2023-05-09
申请号：US17496399
申请日：2021-10-07
CPC分类号： G06F11/1666 , G06F11/1068 , G11C29/42 , G11C29/44 , G11C29/52 , G11C29/70 , G11C29/76 , G11C2029/1204
摘要： A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.
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公开(公告)号：US11264077B2
公开(公告)日：2022-03-01
申请号：US17150514
申请日：2021-01-15
IPC分类号： G11C5/14 , G11C11/4074 , G11C5/04 , G11C29/00
摘要： A memory subsystem is disclosed comprising at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator receiving a power supply signal from a system power supply and outputting two or more power signals, each power signal providing a different, regulated voltage, which regulated voltages are each routed to each of the memory chips; and a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltages which are the same voltages as the voltages output by the voltage regulator on the memory module, and supplying the two or more signals to the memory module.
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公开(公告)号：US11200112B1
公开(公告)日：2021-12-14
申请号：US17000974
申请日：2020-08-24
摘要： A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.
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公开(公告)号：US10606713B2
公开(公告)日：2020-03-31
申请号：US15860875
申请日：2018-01-03
摘要： A technique relates to operating a memory controller. A feedback mode is initiated such that an identified memory device of first memory devices includes an identified bit lane on a data bus to be utilized for testing. A process includes sending commands on the 1-N bit lanes of the command address bus to a buffer and duplicating commands designated for a selected one of the 1-N bit lanes. The process includes sending the duplicated commands on the identified bit lane in route to the buffer, and receiving a result of a parity check for the commands sent on the 1-N bit lanes, such that when the result is a pass the process ends. When the result is a fail, a duplicated parity check is performed using duplicated commands on the identified bit lane in place of the selected one. When the duplicated parity check passes, the selected one is bad.
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公开(公告)号：US10534545B2
公开(公告)日：2020-01-14
申请号：US15847954
申请日：2017-12-20
发明人： Diyanesh B. Chinnakkonda Vidyapoornachary , John B. DeForge , Warren E. Maule , Kirk D. Peterson , Sridhar H. Rangarajan , Saravanan Sethuraman
摘要： An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller.
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7.发明授权公开(公告)号：US10395698B2
公开(公告)日：2019-08-27
申请号：US15825894
申请日：2017-11-29
发明人： Steven R. Carlough , Susan M. Eickhoff , Warren E. Maule , Patrick J. Meaney , Stephen J. Powell , Gary A. Van Huben , Jie Zheng
摘要： One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.
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公开(公告)号：US20190227886A1
公开(公告)日：2019-07-25
申请号：US15875136
申请日：2018-01-19
摘要： A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.
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公开(公告)号：US20190187915A1
公开(公告)日：2019-06-20
申请号：US15847954
申请日：2017-12-20
发明人： Diyanesh B. Chinnakkonda Vidyapoornachary , John B. DeForge , Warren E. Maule , Kirk D. Peterson , Sridhar H. Rangarajan , Saravanan Sethuraman
摘要： An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller.
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公开(公告)号：US10304560B2
公开(公告)日：2019-05-28
申请号：US15255368
申请日：2016-09-02
IPC分类号： G11C29/00 , G06F11/10 , G06F12/1009 , G06F12/0871 , G06F3/06
摘要： Performing error correction in computer memory including receiving a read request targeting a read address within the computer memory; accessing a mark table comprising a plurality of entries, each entry including a field specifying a region size, a field specifying a match address, and a field specifying a mark location; performing a lookup of the mark table using the read address including, for each entry in the mark table: generating a mask based on the region size stored in the entry; determining, based on the mask, whether the read address is within a memory region specified by the match address and region size stored in the entry; and if the read address is within the memory region specified by the match address and region size stored in the entry, performing error correction using the mark location stored in the entry.
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